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chipsalliance / Cores-SweRV_fpga

Apache License 2.0
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Routing issue when implement SweRV Core in Zedboard #7

Open kingstone1927 opened 4 years ago

kingstone1927 commented 4 years ago

Hello,

I tried to implement the SweRV Core in Zedboard fpga and ran into a routing issue when run implementation. The issue is as below:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, 
you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. 
However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_ibufg] >

    ibufg_jtag_tck (IBUF.O) is locked to IOB_X0Y29
     and jtag_tck_ibufg_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

Had anyone implemented the Core SweRV on a different fpga and had the same issue? I tried many forum for resolution but seem like there is no good answer for this. Thanks in advance

olofk commented 2 years ago

SweRVolf is now supported on the Nexys A7 and Basys3 boards. Perhaps you can look at that to get a better idea of the work needed to port to a new board