cjhonlyone / ADC-lvds

Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS

GNU General Public License v3.0

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ADC General LVDS Interface

Generate IP

(vivado) cd ./ip
(vivado) source adc_lvds_ip.tcl

(bash) vivado -mode tcl -source ./ip/adc_lvds_ip.tcl

2 wire mode

ADC3441/ADC3442/ADC3443/ADC3444
1:14 Serdes has been tested

1 wire mode

AD9252, 8 Channel
1:14 Serdes has been tested
1:12 Serdes has been tested

1 wire mode

LTC2263, 2 Channel
1:14 Serdes has been tested