PR to prepare for changes to sectorprocessor on FPGA 1 that enables the merging and streaming of TPAR and AS words to FPGA2. Interface of sector processor is changed from a read of BRAMs containing those words to a FIFO-like output stream.
Opening as a draft to check CI and work out merging.
some bugs in simulation right now, AllStubs not streaming properly and some extra truncation.
PR to prepare for changes to sectorprocessor on FPGA 1 that enables the merging and streaming of TPAR and AS words to FPGA2. Interface of sector processor is changed from a read of BRAMs containing those words to a FIFO-like output stream.
Opening as a draft to check CI and work out merging.
some bugs in simulation right now, AllStubs not streaming properly and some extra truncation.