cornell-zhang / FracBNN

FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
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FracBNN

This repository serves as the official code release of the paper FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations (pubilished at FPGA 2021).

FracBNN, as a binary neural network, achieves MobileNetV2-level accuracy by leveraging fractional activations. In the meantime, its input layer is binarized using a novel thermometer encoding with minimal accuracy degradation, which improves the hardware resource efficiceny.

Citation

If FracBNN helps your research, please consider citing:

@article{Zhang2021fracbnn,
    title = "{FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations}",
    author = {Zhang, Yichi and Pan, Junhao and Liu, Xinheng and Chen, Hongzheng and Chen, Deming and Zhang, Zhiru},
    journal = {The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
    year = {2021}
}

Structure

|   cifar10.py (training script)
|   imagenet.py (training script)
|
└── models/
|   |   fracbnn_cifar10.py
|   |   fracbnn_imagenet.py
|
└───utils/
|   |   quantization.py
|   |   utils.py
|
└───xcel-cifar10/
|   |   High-level synthesis code for FracBNN CIFAR-10 accelerator
|
└───xcel-imagenet/
|   |   High-level synthesis code for FracBNN ImageNet accelerator

Dependency

Python 3.6.8
torch 1.6.0
torchvision 0.7.0
numpy 1.16.4

Run

Pretrained Model Release

Test Only

Train (Two Step Training):

Please refer to the paper for details such as hyperparameters.

Model Accuracy

Dataset Precision (W/A) 1-bit Input Layer Top-1 %
CIFAR-10 1/1.4 (PG) Yes 89.1
ImageNet 1/1.4 (PG) Yes 71.7

CIFAR-10 Accelerator

Compile the HLS code

cd ./xcel-cifar10/source/
make hls

Generate the Bitstream

This step should be done after compiling the HLS code. Assume you are in the directory of ./xcel-cifar10/source/.

make vivado

Deploy on Xilinx Ultra96v2

To test the bitstream on the board, the following files (sample images and labels) are needed:

To deploy the bitstream:

ImageNet Accelerator

Compile HLS and Generate Bitstream

Please run the compilation flow using Vivado HLS. The top function is FracNet() in xcel-imagenet/source/bnn.cc.

Deploy on Xilinx Ultra96v2

To test the bitstream on the board, the following files (sample images, weights) are needed:

To deploy the bitstream: