ctag-fh-kiel
commented
3 years ago This is a strange error message, I have never seen it. Probably a hardware issue. Did you configure for 16MB flash size with menuconfig (this should be done)?
On Tue, Aug 31, 2021 at 9:02 AM guytaylor @.***> wrote:
Hi there, I am having an issue trying to flash my strampler. From what I have read online, it would appear to be a hardware issue. Do you think this could be the case from the logs? Thanks
This is what the esptool.py output looks like, followed by a fuse summary:
PS M:uBoms\Strampler\ctag-straempler-master\bin> esptool.py --chip esp32 --port COM9 --before default_reset --after hard_reset write_flash -z --flash_mode dio --flash_freq 80m --flash_size detect 0x1000 bootloader.bin 0x10000 smplr.bin 0x8000 partitions.bin esptool.py v3.1-dev Serial port COM9 Connecting.... Chip is ESP32-D0WD (revision 1) Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None Crystal is 40MHz MAC: ac:67:b2:5b:ae:a4 Uploading stub... Running stub... Stub running... Configuring flash size... Warning: Could not auto-detect Flash size (FlashID=0x0, SizeID=0x0), defaulting to 4MB Flash will be erased from 0x00001000 to 0x00006fff... Flash will be erased from 0x00010000 to 0x00115fff... Flash will be erased from 0x00008000 to 0x00008fff... Flash params set to 0x022f Compressed 24064 bytes to 14974... Writing at 0x00001000... (100 %) A fatal error occurred: Timed out waiting for packet header PS M:uBoms\Strampler\ctag-straempler-master\bin> espefuse.py --port COM9 summary Connecting.... Detecting chip type... ESP32 espefuse.py v3.1-dev EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
Calibration fuses: BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0) ADC_VREF (BLOCK0): Voltage reference calibration = 1149 R/W (0b00111)
Config fuses: XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0) XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0) XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0) CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 54 R/W (0x36) SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000) SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000) SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000) SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0b00000) SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000) DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)
Efuse fuses: WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000) RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0) CODING_SCHEME (BLOCK0): Efuse variable block length scheme = NONE (BLK1-3 len=256 bits) R/W (0b00) KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)
Identity fuses: MAC (BLOCK0): Factory MAC Address = ac:67:b2:5b:ae:a4 (CRC 0xb1 OK) R/W MAC_CRC (BLOCK0): CRC8 for factory MAC address = 177 R/W (0xb1) CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1) CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0) CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10) CHIP_PACKAGE (BLOCK0): Chip package identifier = 1 R/W (0b001) MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)
Security fuses: FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000) UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0) FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0) CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1) ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0) ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0) JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0) DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0) DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0) DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0) BLOCK1 (BLOCK1): Flash encryption key = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK2 (BLOCK2): Secure boot key = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK3 (BLOCK3): Variable Block 3 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).
— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub https://github.com/ctag-fh-kiel/ctag-straempler/issues/14, or unsubscribe https://github.com/notifications/unsubscribe-auth/ABZMGRV32U7U7WSQK4CB3WLT7R5APANCNFSM5DDNUT3A . Triage notifications on the go with GitHub Mobile for iOS https://apps.apple.com/app/apple-store/id1477376905?ct=notification-email&mt=8&pt=524675 or Android https://play.google.com/store/apps/details?id=com.github.android&referrer=utm_campaign%3Dnotification-email%26utm_medium%3Demail%26utm_source%3Dgithub.
guytaylor
Hi there, I am having an issue trying to flash my strampler. From what I have read online, it would appear to be a hardware issue. Do you think this could be the case from the logs? Thanks
This is the chip I am using, which seems to have the Flash onboard: https://au.mouser.com/ProductDetail/356-ESP32-WROVER-IB
This is what the esptool.py output looks like, followed by a fuse summary:
PS M:_uBoms_\Strampler\ctag-straempler-master\bin> esptool.py --chip esp32 --port COM9 --before default_reset --after hard_reset write_flash -z --flash_mode dio --flash_freq 80m --flash_size detect 0x1000 bootloader.bin 0x10000 smplr.bin 0x8000 partitions.bin esptool.py v3.1-dev Serial port COM9 Connecting.... Chip is ESP32-D0WD (revision 1) Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None Crystal is 40MHz MAC: ac:67:b2:5b:ae:a4 Uploading stub... Running stub... Stub running... Configuring flash size... Warning: Could not auto-detect Flash size (FlashID=0x0, SizeID=0x0), defaulting to 4MB Flash will be erased from 0x00001000 to 0x00006fff... Flash will be erased from 0x00010000 to 0x00115fff... Flash will be erased from 0x00008000 to 0x00008fff... Flash params set to 0x022f Compressed 24064 bytes to 14974... Writing at 0x00001000... (100 %) A fatal error occurred: Timed out waiting for packet header
PS M:_uBoms_\Strampler\ctag-straempler-master\bin> espefuse.py --port COM9 summary Connecting.... Detecting chip type... ESP32 espefuse.py v3.1-dev EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
Calibration fuses: BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0) ADC_VREF (BLOCK0): Voltage reference calibration = 1149 R/W (0b00111)
Config fuses: XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0) XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0) XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0) CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 54 R/W (0x36) SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000) SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000) SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000) SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0b00000) SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000) DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)
Efuse fuses: WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000) RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0) CODING_SCHEME (BLOCK0): Efuse variable block length scheme = NONE (BLK1-3 len=256 bits) R/W (0b00) KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)
Identity fuses: MAC (BLOCK0): Factory MAC Address = ac:67:b2:5b:ae:a4 (CRC 0xb1 OK) R/W MAC_CRC (BLOCK0): CRC8 for factory MAC address = 177 R/W (0xb1) CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1) CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0) CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10) CHIP_PACKAGE (BLOCK0): Chip package identifier = 1 R/W (0b001) MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)
Security fuses: FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000) UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0) FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0) CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1) ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0) ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0) JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0) DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0) DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0) DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0) BLOCK1 (BLOCK1): Flash encryption key = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK2 (BLOCK2): Secure boot key = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK3 (BLOCK3): Variable Block 3 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).