RISC-V switch of QtMips project

[ppisa]

• [x] Update memory model
  • [x] User read and write methods with void pointer and variable buffer size (easier for mmap, for system calls emulation, ELF image writing to memory)
  • [x] Use plain byte addressable backend - it allows to support big and little endian architectures easier and mix of endianness between emulated CPU and host
  • [x] Update cache to work above new model
  • [x] Update peripherals to work above new model, add endian switch to memory backend and frontend objects
• [x] Introduce Address a RegisterValue types to allow 64-bit RISC-V support one day
• [x] Move components to "src" subdirectory
• [x] RISC-V core
  • [x] Rename objects and file names to be more architecture neutral or switch to RISC-V names
  • [x] Decide source of instruction encoding (QtMips used GNU binutils, C converted by Python to Python, then Python simarch )
  • [x] Switch field names to match RISC-V ISA documents
  • [x] Rewrite ALU to support RISC-V operations and GPR file
  • [ ] Consider floating point data path and vector unit communication with GPR
  • [ ] (#128)
  • [ ] Double precision
  • [ ] Vector instructions
  • [x] #27
  • [x] Update interstage buffers/registers in machine::Core
  • [x] instruction arguments description ArgumentDesc
  • [x] Unit for immediate decode
  • [x] Switch/generate RISC-V instruction description table
  • [x] Update branch processing, switch to flush after branch, decide where to process branches (Decode or Execute after ALU)
  • [ ] Decode instruction length (Compressed code) and appropriate PC increment
  • [x] Replace COP0 by machine registers
  • [x] Update resolution of exceptions
  • [x] Update unit tests
  • [x] Update complex assembler based testcases
• [ ] Update core visualization
  • [x] Update existing core visualization to roughly match RISC-V
  • [x] Consider switch of core visualization to SvgScene, old one
  • [x] Update memory view - NOTHING TO DO
  • [x] Update register views
  • [ ] Update instruction view, what to to with 16/32 bit resync
  • [ ] DWARF mapping between instruction address and source line
• [ ] Update templates and examples
  • [ ] Add more advanced examples into repository.
  • [ ] Build examples with CMake ???
• [ ] System calls emulation update
  • [ ] Switch stream/file backends to QIODevice
  • [ ] Update serial port to QIODevice
  • [ ] Update systemcalls to QIODevice
  • [x] Update systemcalls to RISC-V codes and parameters, get rid of delay slot
  • [ ] Rewrite mmap to utilize new memory model and map real files on Linux and Windows
• [ ] Update all documentation and teaching materials
  • [x] Update README
  • [x] Update B35APO pages
• [ ] Packaging and make system
  • [x] CMake
  • [x] Test on Linux
  • [x] Test on Emscripten
  • [x] Test on Windows MingW
  • [x] Test on MacOS
  • [x] SUSE Open Build service
  • [x] UBUNTU Lauchpad
  • [x] Nix
  • [x] Guix
  • [ ] macOS (brew)
  • [ ] ??? for Window (choco?, winget?, store?, pkg)
• [ ] Advanced topics
  • [x] Branch predictor
  • [x] L2/Ln cache
  • [ ] MMU
  • [ ] Multicore
  • [ ] Extend cache states for MESI/MOESI
  • [ ] Visualization of coherence protocols
  • [ ] Visualization of instruction decode (fields)