Machine: fix parse_csr_address

cvut / qtrvsim

RISC-V CPU simulator for education purposes

GNU General Public License v3.0

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Closed trdthg closed 2 months ago

trdthg commented 4 months ago

fix mtval2 will be treated as mtval unexpected.

jdupak commented 4 months ago

The changes look good, but I don't understand the PR message. Can you elaborate?

trdthg commented 4 months ago

for example, csrrwi x16, mtval2, 0x6's second operand will be parsed to mtval

they have the same start