cvut / qtrvsim

RISC-V CPU simulator for education purposes
GNU General Public License v3.0
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implement some FP32 instructions (fadd.s, fsub.s, flw, fsw) #134

Open Jingqing3948 opened 4 months ago

Jingqing3948 commented 4 months ago

This pr is the follow up of https://github.com/cvut/qtrvsim/pull/109.

Sry that because I didn't pass the test cases, I reviewed the code again and accidentally lost the last pr. Thanks to the help of @trdthg , he helped me to modify the test cases (because origin misa register stores supported extensions, so RVF is also needed to be add to misa?)

Now the code can pass the CI for now, and successfully execute those FP instructions.