Recreate unitests for RISC-V

cvut / qtrvsim

RISC-V CPU simulator for education purposes

GNU General Public License v3.0

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Recreate unitests for RISC-V #7

Open jdupak opened 2 years ago

jdupak commented 2 years ago

Modify the unit tests present in https://github.com/cvut/qtrvsim/tree/master/src/machine/tests to work with RISC-V.

Implement each tested component in separate file. See https://github.com/cvut/qtrvsim/blob/master/src/machine/execute/alu.test.h and https://github.com/cvut/qtrvsim/blob/master/src/machine/CMakeLists.txt:94.
Memory and cache should be OK, just move it.

jdupak commented 2 years ago

I have done the moving so now we just need to fix the changed tests. It is prepared in branch rv-tests.

[x] cache
[x] memory
[x] registers
[ ] instruction
[ ] program_loader
[x] core

ppisa commented 2 years ago

The all original complex core tests has been switched to RISC-V, see a9c15510cfad494dc98b9ab9e4ad7b3daddf63d3 and 043fbb17e3e91e08d03a3cfe8ef453ee4d40d846

ppisa commented 1 year ago

Memory tests re-enabled and extended b1f16dbbde2fe7d551f8500a341591d03e7f718d