Closed N0tACyb0rg closed 1 year ago
cyring
commented
1 year ago According to the crash:
[ 619.939065] RIP: 0010:BaseClock_Core+0xe/0x90 [corefreqk]
[ 619.939109] RAX: ffffffffc18e0510 RBX: 000000000000000b RCX: 00000000000000cd... MSR_FSB_FREQ (0x00000000000000cd) appears to be not supported on Goldmont Plus
Can you check its support as bellow ?
rdmsr -ax 0xcdCan you also provide me the CPUID from /proc/cpuinfo ?
I just need cpu family model stepping model name from first CPU
N0tACyb0rg
commented
1 year ago Unfortunately it is not supported: rdmsr: CPU 0 cannot read MSR 0x000000cd
N0tACyb0rg
commented
1 year ago Here's the output of cat /proc/cpuinfo:
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 122
model name : Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz
stepping : 1
microcode : 0x3c
cpu MHz : 2647.387
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 0
cpu cores : 4
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 24
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave rdrand lahf_lm 3dnowprefetch cpuid_fault cat_l2 pti cdp_l2 ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust smep erms mpx rdt_a rdseed smap clflushopt intel_pt sha_ni xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts umip rdpid md_clear arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs ept_mode_based_exec tsc_scaling
bugs : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass
bogomips : 2189.00
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:
processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 122
model name : Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz
stepping : 1
microcode : 0x3c
cpu MHz : 2586.523
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 1
cpu cores : 4
apicid : 2
initial apicid : 2
fpu : yes
fpu_exception : yes
cpuid level : 24
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave rdrand lahf_lm 3dnowprefetch cpuid_fault cat_l2 pti cdp_l2 ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust smep erms mpx rdt_a rdseed smap clflushopt intel_pt sha_ni xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts umip rdpid md_clear arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs ept_mode_based_exec tsc_scaling
bugs : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass
bogomips : 2189.00
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:
processor : 2
vendor_id : GenuineIntel
cpu family : 6
model : 122
model name : Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz
stepping : 1
microcode : 0x3c
cpu MHz : 2586.326
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 2
cpu cores : 4
apicid : 4
initial apicid : 4
fpu : yes
fpu_exception : yes
cpuid level : 24
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave rdrand lahf_lm 3dnowprefetch cpuid_fault cat_l2 pti cdp_l2 ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust smep erms mpx rdt_a rdseed smap clflushopt intel_pt sha_ni xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts umip rdpid md_clear arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs ept_mode_based_exec tsc_scaling
bugs : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass
bogomips : 2189.00
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:
processor : 3
vendor_id : GenuineIntel
cpu family : 6
model : 122
model name : Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz
stepping : 1
microcode : 0x3c
cpu MHz : 2586.694
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 3
cpu cores : 4
apicid : 6
initial apicid : 6
fpu : yes
fpu_exception : yes
cpuid level : 24
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave rdrand lahf_lm 3dnowprefetch cpuid_fault cat_l2 pti cdp_l2 ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust smep erms mpx rdt_a rdseed smap clflushopt intel_pt sha_ni xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts umip rdpid md_clear arch_capabilities
vmx flags : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs ept_mode_based_exec tsc_scaling
bugs : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass
bogomips : 2189.00
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:cpu family : 6
model : 122
model name : Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz
stepping : 1which make a CPUID 06_7A (hexa)
aka [Gemini Lake]
https://github.com/cyring/CoreFreq/blob/5a84d5fc8d7dce149e547349c7971d7af5c49128/corefreqk.h#L1825
Entry starts here: https://github.com/cyring/CoreFreq/blob/5a84d5fc8d7dce149e547349c7971d7af5c49128/corefreqk.h#L8731
... and first access register is MSR_PLATFORM_INFO in function Query_Goldmont
https://github.com/cyring/CoreFreq/blob/5a84d5fc8d7dce149e547349c7971d7af5c49128/corefreqk.c#L6730
Question: can you access these registers ?
## MSR_PLATFORM_INFO
rdmsr -ax 0xCE
## MSR_IA32_APICBASE
rdmsr -ax 0x1B
## MSR_RAPL_POWER_UNIT
rdmsr -ax 0x606
## MSR_PKG_POWER_INFO
rdmsr -ax 0x614MSR_PLATFORM_INFO: 40821f0010b00 x4
MSR_IA32_APICBASE:
fee00d00
fee00c00
fee00c00
fee00c00MSR_RAPL_POWER_UNIT: 330a0e08 x4
MSR_PKG_POWER_INFO: 600 x4
cyring
commented
1 year ago I need the first crash log.
Can you please run again without ArchID. I mean just a basic insmod corefreqk.ko
then post the kernel log from RIP to </TASK>.
N0tACyb0rg
commented
1 year ago I couldn't recover an actual log since the kernel panicked, but here is a picture of my screen when I ran insmod on tty3:
cyring
commented
1 year ago Oh MSR_TURBO_ACTIVATION_RATIO is not available on GDM+
Can you try:
rdmsr -ax 0x64CIt cannot read that register.
cyring
commented
1 year ago In function PerCore_Goldmont_Query() of corefreqk.c file, please comment Intel_Turbo_Activation_Ratio
https://github.com/cyring/CoreFreq/blob/5a84d5fc8d7dce149e547349c7971d7af5c49128/corefreqk.c#L12017
static void PerCore_Goldmont_Query(void *arg)
{
/*
Intel_Turbo_Activation_Ratio(Core);
*/
}Save, rebuild, try
make clean all
insmod corefreqk.koThat resolved the issue! insmod worked immediately and CoreFreq is now working!
cyring
commented
1 year ago That resolved the issue!
insmodworked immediately and CoreFreq is now working!
I believe it's the first time seeing CoreFreq with your architecture because this MSR is mentioned compatible since Goldmont (non Plus)
Do you have any option in BIOS which prevents from using it ?
N0tACyb0rg
commented
1 year ago I don't believe so. Intel TurboBoost is enabled.
cyring
commented
1 year ago I don't believe so. Intel TurboBoost is enabled.
OK, I'm programming a specific entry for GDM Plus...
N0tACyb0rg
commented
1 year ago Cool!
cyring
commented
1 year ago For your testings you can now pull the develop branch to get the fix.
Could you fulfill a Wiki support of your processor ?
You can take as an example one of those intel-laptops entries.
At least corefreq-cli -s -n -m -n -M -n -C 1 -n -c 1 -n -g 1
N0tACyb0rg
commented
1 year ago Latest commit is working as expected, thanks! Also, here is my gist for the wiki page: https://gist.github.com/N0tACyb0rg/c34b592adb6507c0fb51b430f56d8627
cyring
commented
1 year ago I should had tell you about the gist page:
Thank you
cyring
commented
1 year ago Remaining issues observed in the output
cyring
commented
1 year ago Can you read this register in two cases: Idle CPU next Loaded CPU
## IA32_PERF_STATUS
rdmsr -ax 0x198Then simply read C-States BAR
## MSR_PMG_IO_CAPTURE_BASE
rdmsr -ax 0x000000e4In [Geminilake] section, change the voltage formula:
https://github.com/cyring/CoreFreq/blob/9e80cbf9828aac23f977a1e650e91213472e9d31/corefreqk.h#L8745
With:
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,Using your dump VID of 6512, you will get a Vcore about 0.7949V
Stress processor and check if the Vcore is matching specs.
cyring
commented
1 year ago For your testings, all pending changes are inside this archive: Be prepared for a crash, save your files before loading the driver.
N0tACyb0rg
commented
1 year ago Alright, I downloaded the provided archive and got it all set up. Everything worked immediately. The only thing I noticed was that the VID value is only displayed on one CPU core (001 to be precise). The vcore is around 0.7949 though. All the voltage stuff is only being listed for one core though (001 again).
Now with the registers, both return values. rdmsr -ax 0x198 returns 268f00001a00 for all cores, and rdmsr -ax 0x000000e4 returns 0 for all cores.
cyring
commented
1 year ago Alright, I downloaded the provided archive and got it all set up. Everything worked immediately. The only thing I noticed was that the VID value is only displayed on one CPU core (001 to be precise). The vcore is around 0.7949 though. All the voltage stuff is only being listed for one core though (001 again).
Now with the registers, both return values.
rdmsr -ax 0x198returns268f00001a00for all cores, andrdmsr -ax 0x000000e4returns 0 for all cores.
Latest Gemini Lake changes are now committed into the develop branch.
Based on MSR IA32_PERF_STATUS[48-32] and formula Vcore = VID / 8192
| VID | Vcore (V) |
|---|---|
6512 |
0.7949 |
9871 |
1.2049 |
You can change, as will, the Voltage scope in the Settings window,
next from Menu or shortcut V, switch to the Voltage view:
Usually the VID is common for the whole Processor package but if your observations reveal discrete voltage per Core or per Thread (SMT) then let me know, I'll make it as a default.
Could you also post here a full output as bellow:
corefreq-cli -s -n -m -n -M -n -C 1 -n -c 1 -n -g 1 -B -n -kand screenshot the main Frequency view next Sensors > Power view while Processor is idled then stressed.
N0tACyb0rg
commented
1 year ago Here is the output from the command:
Processor [Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz]
|- Architecture [Gemini Lake]
|- Vendor ID [GenuineIntel]
|- Microcode [0x0000003c]
|- Signature [ 06_7A]
|- Stepping [ 1]
|- Online CPU [ 4/ 4]
|- Base Clock [ 99.468]
|- Frequency (MHz) Ratio
Min 795.72 < 8 >
Max 1094.12 < 11 >
|- Factory [100.000]
1100 [ 11 ]
|- Performance
|- P-State
TGT 795.72 < 8 >
|- Turbo Boost [ LOCK]
1C 2685.56 < 27 >
2C 2586.10 < 26 >
3C 2586.10 < 26 >
4C 2586.10 < 26 >
|- Uncore [ LOCK]
|- TDP Level [ 0:0 ]
|- Programmable [ LOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ LOCK]
Turbo AUTO [ 0 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [N] AES [Y] AVX/AVX2 [N/N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [N] MOVDIRI [N] MOVDIR64B [N]
|- BMI1/BMI2 [N/N] CLWB [N] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [N] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- ENQCMD [N] GFNI [N] OSPKE [N] WAITPKG [N]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [Y] SGX [Y]
|- VAES [N] VPCLMULQDQ [N] PREFETCH/W [Y] LZCNT [N]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast Short REP CMPSB FSRC [Missing]
|- Fast Short REP MOVSB FSRM [Missing]
|- Fast Short REP STOSB FSRS [Missing]
|- Fast Zero-length REP MOVSB FZRM [Missing]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA | FMA4 [Missing]
|- Hardware Feedback Interface HFI [Missing]
|- Hardware Lock Elision HLE [Missing]
|- History Reset HRESET [Missing]
|- Hybrid part processor HYBRID [Missing]
|- Instruction Based Sampling IBS [Missing]
|- Instruction INVPCID INVPCID [Missing]
|- Long Mode 64 bits IA64 | LM [Capable]
|- Linear Address Masking LAM [Missing]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Capable]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Platform Configuration PCONFIG [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Write Data to a Processor Trace Packet PTWRITE [Capable]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Thread Director TD [Missing]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Missing]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [ Enable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [ Unable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [ Enable]
|- Arch - Buffer Overwriting MD-CLEAR [Capable]
|- Arch - No Rogue Data Cache Load RDCL_NO [Capable]
|- Arch - Enhanced IBRS IBRS_ALL [Capable]
|- Arch - Return Stack Buffer Alternate RSBA [Capable]
|- Arch - No Speculative Store Bypass SSB_NO [Capable]
|- Arch - No Microarchitectural Data Sampling MDS_NO [ Enable]
|- Arch - No TSX Asynchronous Abort TAA_NO [Capable]
|- Arch - No Page Size Change MCE PSCHANGE_MC_NO [ Enable]
|- Arch - STLB QoS STLB [ Unable]
|- Arch - Functional Safety Island FuSa [ Unable]
|- Arch - RSM in CPL0 only RSM [ Unable]
|- Arch - Split Locked Access Exception SPLA [ Unable]
|- Arch - Snoop Filter QoS Mask SNOOP_FILTER [ Unable]
|- Arch - No Fast Predictive Store Forwarding PSFD [ Unable]
|- Arch - Data Operand Independent Timing Mode DOITM [ Unable]
|- Arch - Not affected by SBDR or SSDP SBDR_SSDP_NO [Capable]
|- Arch - No Fill Buffer Stale Data Propagator FBSDP_NO [Capable]
|- Arch - No Primary Stale Data Propagator PSDP_NO [Capable]
|- Arch - Overwrite Fill Buffer values FB_CLEAR [Capable]
|- Arch - Special Register Buffer Data Sampling SRBDS [ Unable]
|- RDRAND and RDSEED mitigation RNGDS [ Unable]
|- Restricted Transactional Memory RTM [ Unable]
|- Verify Segment for Writing instruction VERW [ Unable]
|- Arch - Restricted RSB Alternate RRSBA [Capable]
|- Arch - No Branch Target Injection BHI_NO [Capable]
|- Arch - Legacy xAPIC Disable XAPIC_DIS [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer PBRSB_NO [Capable]
|- Arch - IPRED disabled for CPL3 IPRED_DIS_U [ Unable]
|- Arch - IPRED disabled for CPL0/1/2 IPRED_DIS_S [ Unable]
|- Arch - RRSBA disabled for CPL3 RRSBA_DIS_U [ Unable]
|- Arch - RRSBA disabled for CPL0/1/2 RRSBA_DIS_S [ Unable]
|- Arch - BHI disabled for CPL0/1/2 BHI_DIS_S [ Unable]
|- No MXCSR Configuration Dependent Timing MCDT_NO [ Unable]
Security Features
|- CPUID Key Locker KL [Missing]
|- AES Key Locker instructions AESKLE [Missing]
|- AES Wide Key Locker instructions WIDE_KL [Missing]
|- Software Guard SGX1 Extensions SGX1 [Missing]
|- Software Guard SGX2 Extensions SGX2 [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW <OFF>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L2 Prefetcher L2 HW <OFF>
|- L2 Line Prefetcher L2 HW CL <OFF>
|- System Management Mode SMM-Dual [OFF]
|- Hyper-Threading HTT [OFF]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost TURBO < ON>
|- Energy Efficiency Optimization EEO <OFF>
|- Race To Halt Optimization R2H <OFF>
|- Watchdog Timer TCO <OFF>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [OFF]
|- Version [ N/A]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 4]
|- Counters: General Fixed
| { 4, 0, 0 } x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E < ON>
|- C1 Auto Demotion C1A <OFF>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U <OFF>
|- C3 UnDemotion C3U <OFF>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < C3>
|- I/O MWAIT Redirection IOMWAIT <Disable>
|- Max C-State Inclusion RANGE < C3>
|- Core C-States
|- C-States Base Address BAR [ 0x0 ]
|- ACPI Processor C-States _CST [ 3]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 0 2 4 2 1 1
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
|- Top-down slots Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 5]
|- Performance Present Capabilities _PPC [ 0]
|- Hardware-Controlled Performance States HWP [OFF]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax < 2:105 C>
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 6 W]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 10 W>
|- Time Window TW1 < 28 s>
|- Power Limit PL2 < 15 W>
|- Time Window TW2 < 976 us>
|- Thermal Design Power Core [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 976 us]
|- Thermal Design Power Uncore [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 976 us]
|- Thermal Design Power DRAM <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Platform [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 976 us]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 976 us]
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Package Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Units
|- Power watt [ 0.000003906]
|- Energy joule [ 0.000000061]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID ID ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 32768 8w 24576 6w 4194304 16w 0 0
001: 0 2 1 0 32768 8w 24576 6w 4194304 16w 0 0
002: 0 4 2 0 32768 8w 24576 6w 4194304 16w 0 0
003: 0 6 3 0 32768 8w 24576 6w 4194304 16w 0 0
Goldmont Plus [31F0]
Controller #0 Dual Channel
Bus Rate 5000 MT/s Bus Speed 4975 MT/s DDR3 Speed 800 MHz
Cha CL RCD RP RAS RRD RFC WR RTPr WTPr FAW B2B CWL CMD REFI
#0 5 5 5 0 4 256 0 4 14 0 0 3 1T 0
#1 5 5 5 0 4 256 0 4 14 0 0 3 1T 0
ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE ECC
#0 4 0 11 0 0 6 0 0 0 4 4 0 0 0
#1 4 0 11 0 0 6 0 0 0 4 4 0 0 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
CPU Freq(MHz) VID Vcore TMP(C) Accumulator Energy(J) Power(W)
000 120.06 0 0.0000 37 000000000000000000 0.000000000 0.000000000
001 89.51 0 0.0000 37 000000000000000000 0.000000000 0.000000000
002 83.53 6553 0.7999 37 000000000000000000 0.000000000 0.000000000
003 102.11 0 0.0000 37 000000000000000000 0.000000000 0.000000000
Package[0] Cores Uncore Memory Platform
Energy(J): 0.002687134 0.000260376 0.000168152 0.000118713 0.000000000
Power(W) : 0.002687134 0.000260376 0.000168152 0.000118713 0.000000000
CPU Freq(MHz) Ratio Turbo C0(%) C1(%) C3(%) C6(%) C7(%) Min TMP:TS Max
000 120.06 ( 1.21) 10.97 8.26 0.30 0.00 90.27 0.00 36 / 37:66 / 42
001 89.51 ( 0.90) 8.18 7.49 0.37 0.00 90.98 0.00 36 / 37:66 / 42
002 83.53 ( 0.84) 7.63 7.06 1.04 0.00 90.78 0.00 36 / 37:66 / 42
003 102.11 ( 1.03) 9.33 7.62 0.84 0.00 90.47 0.00 36 / 37:66 / 42
Averages: Turbo C0(%) C1(%) C3(%) C6(%) C7(%) TjMax: Pkg:
9.03 7.61 0.64 0.00 90.62 0.00 105 C 37 C
Cycles State(%)
PC02 1005594 0.36
PC03 0 0.00
PC04 0 0.00
PC06 594711780 44.98
PC07 0 0.00
PC08 0 0.00
PC09 0 0.00
PC10 0 0.00
MC6 0 0.00
PTSC 1094620967
UNCORE 0
[ 0] Dell Inc.
[ 1] 1.23.0
[ 2] 10/04/2022
[ 3] Dell Inc.
[ 4] Latitude 3190 2-in-1
[ 5]
[ 6] H---M--
[ 7] 081F
[ 8] Latitude
[ 9] Dell Inc.
[10] 0057FT
[11] A00
[12] /---L---/---M---9---6---
[13] Number Of Devices:2\Maximum Capacity:8388608 bytes
[14] A1_DIMM0\A1_BANK0
[15]
[16]
[17]
[18] Hynix
[19]
[20]
[21]
[22] 0000000000-00000
[23]
[24]
[25]
Linux:
|- Release [6.1.1-arch1-1]
|- Version [#1 SMP PREEMPT_DYNAMIC Wed, 21 Dec 2022 22:27:55 +0000]
|- Machine [x86_64]
Memory:
|- Total RAM 7952036 KB
|- Shared RAM 931792 KB
|- Free RAM 724500 KB
|- Buffer RAM 56308 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < tsc>
CPU-Freq driver [ intel_cpufreq]
Governor [ schedutil]
CPU-Idle driver [ intel_idle]
|- Idle Limit [ C10]
|- State POLL C1 C1E C6 C7s C8 C9 C10
|- CPUIDLE MWAIT 0 MWAIT 0 MWAIT 0 MWAIT 0 MWAIT 0 MWAIT 0 MWAIT 0
|- Power -1 0 0 0 0 0 0 0
|- Latency 0 2 10 150 150 5963 5963 6291
|- Residency 0 2 20 150 150 5963 5963 6291 And here are the screenshots:
Idle:
Stressed:
N0tACyb0rg
commented
1 year ago Also, does this suffice? New Gist
cyring
commented
1 year ago N0tACyb0rg
commented
1 year ago The memory controller output is quite confusing to me. Here is a table of the specifications I was able to find from Dell (the maker of my laptop):
I have the 8 GB configuration.
N0tACyb0rg
commented
1 year ago With the Vcore, I was reading on the package level.
cyring
commented
1 year ago With the Vcore, I was reading on the package level.
You mean the Vcore always remains at 0.7999V whatever the processor load is ?
If not, can you please show me when it reaches its max value. I would like some screenshots of the Voltage view, like those:
Remarks:
O will provide you integrated stress functions.F10 will stop an on-going stress loopcyring
commented
1 year ago The memory controller output is quite confusing to me. Here is a table of the specifications I was able to find from Dell (the maker of my laptop):
So the SilverMont decoder does not work with N5000.
Let's try with other 14 nm Skylake architecture decoder.
PCI_Geminilake_ids at lines:https://github.com/cyring/CoreFreq/blob/1382c9011a744ff8290078b239c6c2681d417edb/corefreqk.h#L2802
... with:
.driver_data = (kernel_ulong_t) SKL_IMChttps://github.com/cyring/CoreFreq/blob/1382c9011a744ff8290078b239c6c2681d417edb/corefreqd.c#L6613
... with:
case DID_INTEL_GEMINILAKE_HB:
SKL_CAP(RO(Shm), RO(Proc), RO(Core));
SKL_IMC(RO(Shm), RO(Proc));
break;Here is the voltage information per-CPU:
Idling:
Stressed:
N0tACyb0rg
commented
1 year ago The changes broke the Memory Controller output:
[caleb@NerdTop CoreFreq]$ ./corefreq-cli -M
GenuineIntel [ 0]
Controller #0 Disabled Here is the voltage information per-CPU: Idling:
Thanks, I clearly see Vcore in its Min, Max bounds. Formula appears correct also.
Specification reference:
cyring
commented
1 year ago The changes broke the Memory Controller output:
[caleb@NerdTop CoreFreq]$ ./corefreq-cli -M GenuineIntel [ 0] Controller #0 Disabled
Programming an IMC decoder will be a long road... First we need the Gemini Lake - Goldmont Plus - Pentium N series datasheet volume 2 with all IMC registers.
N0tACyb0rg
commented
1 year ago Would this work? Potential Datasheet
N0tACyb0rg
commented
1 year ago I found items about the memory controller on page 71 of that PDF.
cyring
commented
1 year ago I found items about the memory controller on page 71 of that PDF.
Unfortunately document is about N3000 series and DDR3
cyring
commented
1 year ago @N0tACyb0rg
Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet - Volume 2 of 2 February 2018 Document Number: 336561-001
Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet Volume 1 of 2 Revision 005 July 2021 Document Number: 336560
cyring
commented
1 year ago It's encouraging: MCHBAR can be remap like I did with Skylake
But some primary timings were not found. Ex: tCL ?
cyring
commented
1 year ago Based on datasheet, I've a bunch of Host Bridge Registers I need them to be dump: are you available for this ?
N0tACyb0rg
commented
1 year ago Yes I am.
cyring
commented
1 year ago Yes I am.
Hello,
You can build this archive where you will just load the kernel module to dump registers.
insmod ./corefreqk.koIn your kernel log you will find numerous lines as bellow:
CoreFreq: ---------------- DUMP START ----------------
CoreFreq: Cap_A[0x%08x] Cap_B[0x%08x]
CoreFreq: IOMMU[%d][0x%016llx]
CoreFreq: 0x%08x 0x%08x 0x%08x 0x%08x
[0x%08x] [0x%08x] [0x%08x] [0x%08x]
...
CoreFreq: 0x%08x 0x%08x 0x%08x 0x%08x
[0x%08x] [0x%08x] [0x%08x] [0x%08x]
CoreFreq: ---------------- DUMP STOP ----------------Here is the dump:
[ 6824.430956] CoreFreq(1:-1:-1): Processor [ 06_7A] Architecture [Gemini Lake] CPU [4/4]
[ 6824.431028] CoreFreq: ---------------- DUMP START ----------------
[ 6824.431043] CoreFreq: Cap_A[0x00000000] Cap_B[0x80000000]
CoreFreq: IOMMU[-1][0xffffffffffffffff]
[ 6824.431065] CoreFreq: 0x00001000 0x00001200 0x00001400 0x00001600
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431072] CoreFreq: 0x00001004 0x00001204 0x00001404 0x00001604
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431077] CoreFreq: 0x00001008 0x00001208 0x00001408 0x00001608
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431083] CoreFreq: 0x0000100c 0x0000120c 0x0000140c 0x0000160c
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431089] CoreFreq: 0x00001010 0x00001210 0x00001410 0x00001610
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431094] CoreFreq: 0x00001014 0x00001214 0x00001414 0x00001614
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431100] CoreFreq: 0x00001018 0x00001218 0x00001418 0x00001618
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431106] CoreFreq: 0x0000101c 0x0000121c 0x0000141c 0x0000161c
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431112] CoreFreq: 0x00001020 0x00001220 0x00001420 0x00001620
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431117] CoreFreq: 0x00001024 0x00001224 0x00001424 0x00001624
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431123] CoreFreq: 0x00001028 0x00001228 0x00001428 0x00001628
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431128] CoreFreq: 0x0000102c 0x0000122c 0x0000142c 0x0000162c
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431134] CoreFreq: 0x00001030 0x00001230 0x00001430 0x00001630
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431139] CoreFreq: 0x00001034 0x00001234 0x00001434 0x00001634
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431145] CoreFreq: 0x00001038 0x00001238 0x00001438 0x00001638
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431151] CoreFreq: 0x0000103c 0x0000123c 0x0000143c 0x0000163c
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431156] CoreFreq: 0x00001040 0x00001240 0x00001440 0x00001640
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431162] CoreFreq: 0x00001044 0x00001244 0x00001444 0x00001644
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431167] CoreFreq: 0x00001048 0x00001248 0x00001448 0x00001648
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431173] CoreFreq: 0x0000104c 0x0000124c 0x0000144c 0x0000164c
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 6824.431175] CoreFreq: ---------------- DUMP STOP ----------------MCHBAR does not map as expected.
Can you please post all device DID ?
lspci -nnI'm reviewing the code to dump but I don't find what's wrong.
This new archive, the function is called DumpMemoryBAR in corefreqk.c file.
Remark: I've removed the IOMMU from the dump. Does not make a difference.
For example, I'm dumping from an Ivy Bridge processor which follows the same rule to remap in kernel space the MCHBAR happening in function Router
Here's the dump:
CoreFreq: ---------------- DUMP START ----------------
CoreFreq: 0x00004000 0x00004400 0x00000000 0x00000000
[0x0018899a] [0x0018899a] [0x00000000] [0x00000000]
CoreFreq: 0x00004004 0x00004404 0x00000000 0x00000000
[0x10248588] [0x10248588] [0x00000000] [0x00000000]
CoreFreq: 0x00004008 0x00004408 0x00000000 0x00000000
[0x0a022220] [0x0a022220] [0x00000000] [0x00000000]
CoreFreq: 0x0000400c 0x0000440c 0x00000000 0x00000000
[0x000058d7] [0x000058d7] [0x00000000] [0x00000000]
CoreFreq: ---------------- DUMP STOP ----------------Major difference is IVB has MCHBAR offsets starting at 0x4000.
Remark: in this example, I'm stopping at 0x4010; max of two possible IMC channels; displacement between channels is 0x400
In Gemini Lake datasheet volume 2, the offsets are specified at 0x1000, displacement is 0x200, I see four channel spaces: 2 for LPDDR4 or 2 for DDR4
So I don't understand why the N5000 dump is full of 0xffffffff
Dump made with Tiger Lake/U
Remark: IMC architecture with two controllers
CoreFreq(2:6:-1): Processor [ 06_8C] Architecture [Tiger Lake/U] SMT [8/8]
resource sanity check: requesting [mem 0xfedc0000-0xfedcffff], which spans more than pnp 00:05 [mem 0xfedc0000-0xfedc7fff]
caller Router+0xd6/0x120 [corefreqk] mapping multiple BARs
CoreFreq: ---------------- DUMP START ----------------
CoreFreq: 0x00004000 0x00004400 0x00000000 0x00000000
[0x03083008] [0x03083008] [0x00000000] [0x00000000]
CoreFreq: 0x00004004 0x00004404 0x00000000 0x00000000
[0x00001038] [0x00001038] [0x00000000] [0x00000000]
CoreFreq: 0x00004008 0x00004408 0x00000000 0x00000000
[0x00210410] [0x00210410] [0x00000000] [0x00000000]
CoreFreq: 0x0000400c 0x0000440c 0x00000000 0x00000000
[0x04040404] [0x04040404] [0x00000000] [0x00000000]
CoreFreq: ---------------- DUMP STOP ----------------
CoreFreq: ---------------- DUMP START ----------------
CoreFreq: 0x00004000 0x00004400 0x00000000 0x00000000
[0x06086016] [0x03083008] [0x00000000] [0x00000000]
CoreFreq: 0x00004004 0x00004404 0x00000000 0x00000000
[0x00002c68] [0x00001038] [0x00000000] [0x00000000]
CoreFreq: 0x00004008 0x00004408 0x00000000 0x00000000
[0x00010822] [0x00210410] [0x00000000] [0x00000000]
CoreFreq: 0x0000400c 0x0000440c 0x00000000 0x00000000
[0x08080408] [0x04040404] [0x00000000] [0x00000000]
CoreFreq: ---------------- DUMP STOP ----------------Now the voodoo thing
MCHBAR from offset 0x48
Shadow MCHBAR from offset 0xd0
Please give a try to this last archive (which maps from the Shadow BAR):
N0tACyb0rg
commented
1 year ago
MCHBARdoes not map as expected. Can you please post all device DID ?lspci -nn
Here is the output:
00:00.0 Host bridge [0600]: Intel Corporation Gemini Lake Host Bridge [8086:31f0] (rev 03)
00:00.1 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor Dynamic Platform and Thermal Framework Processor Participant [8086:318c] (rev 03)
00:00.2 Non-Essential Instrumentation [1300]: Intel Corporation Celeron/Pentium Silver Processor NorthPeak [8086:318e] (rev 03)
00:02.0 VGA compatible controller [0300]: Intel Corporation GeminiLake [UHD Graphics 605] [8086:3184] (rev 03)
00:0e.0 Audio device [0403]: Intel Corporation Celeron/Pentium Silver Processor High Definition Audio [8086:3198] (rev 03)
00:0f.0 Communication controller [0780]: Intel Corporation Celeron/Pentium Silver Processor Trusted Execution Engine Interface [8086:319a] (rev 03)
00:11.0 Unclassified device [0050]: Intel Corporation Celeron/Pentium Silver Processor Integrated Sensor Solution [8086:31a2] (rev 03)
00:12.0 SATA controller [0106]: Intel Corporation Celeron/Pentium Silver Processor SATA Controller [8086:31e3] (rev 03)
00:13.0 PCI bridge [0604]: Intel Corporation Gemini Lake PCI Express Root Port [8086:31d8] (rev f3)
00:15.0 USB controller [0c03]: Intel Corporation Celeron/Pentium Silver Processor USB 3.0 xHCI Controller [8086:31a8] (rev 03)
00:16.0 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor I2C 0 [8086:31ac] (rev 03)
00:16.1 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor I2C 1 [8086:31ae] (rev 03)
00:16.2 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor I2C 2 [8086:31b0] (rev 03)
00:16.3 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor I2C 3 [8086:31b2] (rev 03)
00:17.0 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor I2C 4 [8086:31b4] (rev 03)
00:17.1 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor I2C 5 [8086:31b6] (rev 03)
00:17.2 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor I2C 6 [8086:31b8] (rev 03)
00:17.3 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor I2C 7 [8086:31ba] (rev 03)
00:18.0 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor Serial IO UART Host Controller [8086:31bc] (rev 03)
00:18.1 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor Serial IO UART Host Controller [8086:31be] (rev 03)
00:18.3 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor Serial IO UART Host Controller [8086:31ee] (rev 03)
00:19.0 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller [8086:31c2] (rev 03)
00:19.1 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller [8086:31c4] (rev 03)
00:19.2 Signal processing controller [1180]: Intel Corporation Celeron/Pentium Silver Processor Serial IO SPI Host Controller [8086:31c6] (rev 03)
00:1c.0 SD Host controller [0805]: Intel Corporation Celeron/Pentium Silver Processor SDA Standard Compliant SD Host Controller [8086:31cc] (rev 03)
00:1f.0 ISA bridge [0601]: Intel Corporation Celeron/Pentium Silver Processor PCI-default ISA-bridge [8086:3197] (rev 03)
01:00.0 Network controller [0280]: Intel Corporation Wireless 8265 / 8275 [8086:24fd] (rev 78)Please give a try to this last archive (which maps from the Shadow BAR):
Here is the new output from the module:
[ 1654.926985] CoreFreq(1:-1:-1): Processor [ 06_7A] Architecture [Gemini Lake] CPU [4/4]
[ 1654.927075] CoreFreq: ---------------- DUMP START ----------------
[ 1654.927080] CoreFreq: 0x00001000 0x00001200 0x00001400 0x00001600
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927086] CoreFreq: 0x00001004 0x00001204 0x00001404 0x00001604
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927092] CoreFreq: 0x00001008 0x00001208 0x00001408 0x00001608
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927098] CoreFreq: 0x0000100c 0x0000120c 0x0000140c 0x0000160c
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927103] CoreFreq: 0x00001010 0x00001210 0x00001410 0x00001610
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927109] CoreFreq: 0x00001014 0x00001214 0x00001414 0x00001614
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927114] CoreFreq: 0x00001018 0x00001218 0x00001418 0x00001618
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927120] CoreFreq: 0x0000101c 0x0000121c 0x0000141c 0x0000161c
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927125] CoreFreq: 0x00001020 0x00001220 0x00001420 0x00001620
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927131] CoreFreq: 0x00001024 0x00001224 0x00001424 0x00001624
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927136] CoreFreq: 0x00001028 0x00001228 0x00001428 0x00001628
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927142] CoreFreq: 0x0000102c 0x0000122c 0x0000142c 0x0000162c
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927148] CoreFreq: 0x00001030 0x00001230 0x00001430 0x00001630
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927153] CoreFreq: 0x00001034 0x00001234 0x00001434 0x00001634
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927159] CoreFreq: 0x00001038 0x00001238 0x00001438 0x00001638
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927164] CoreFreq: 0x0000103c 0x0000123c 0x0000143c 0x0000163c
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927170] CoreFreq: 0x00001040 0x00001240 0x00001440 0x00001640
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927176] CoreFreq: 0x00001044 0x00001244 0x00001444 0x00001644
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927181] CoreFreq: 0x00001048 0x00001248 0x00001448 0x00001648
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927187] CoreFreq: 0x0000104c 0x0000124c 0x0000144c 0x0000164c
[0xffffffff] [0xffffffff] [0xffffffff] [0xffffffff]
[ 1654.927189] CoreFreq: ---------------- DUMP STOP ----------------
System Info:
I compiled from the develop branch with the provided make command for Intel systems:
make MSR_CORE_PERF_UC=MSR_CORE_PERF_FIXED_CTR1 MSR_CORE_PERF_URC=MSR_CORE_PERF_FIXED_CTR2. I then attempted to insertcorefreqk.kousingsudo insmod corefreqk.koand got a kernel panic. I tried testing it by inserting it using the suggestion in #227,sudo insmod corefreqk.ko ArchID=11and got a segmentation fault instead of a kernel panic. Here's the log for that from dmesg: pastebin.