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d953i / Custom_Part_Data_Files

Xilinx PCIe to MIG DDR4 example designs and custom part data files
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Error when doing source Custom_Part_Data_Files-master/Boards/Xilinx_BCU1525/create_project.tcl #4

Closed wmand closed 9 months ago

wmand commented 9 months ago

Hi

I received error when doing source Custom_Part_Data_Files-master/Boards/Xilinx_BCU1525/create_project.tcl

and Error as follows

create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0

ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:ip:util_ds_buf:2.2 ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

while executing

"create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0" (file "Custom_Part_Data_Files-master/Boards/Xilinx_BCU1525/create_project.tcl" line 68) INFO: [Common 17-17] undo 'startgroup' update_compile_order -fileset sources_1

Any idea on how to fix it ?

Thanks

d953i commented 9 months ago

Try latest Vivado version 2023.2 or change util_ds_buf IP version to 2.1

wmand commented 9 months ago

Thank you I changed ds_buf_IP version to 2.1 and be able to synthetize, implementation and generate bitstrea,