d953i / Custom_Part_Data_Files

Xilinx PCIe to MIG DDR4 example designs and custom part data files
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axi bcu1525 calibration csv ddr ddr4 dimm fpga mig rdimm sodimm sqrl tcl udimm vcu1525 verilog vivado xilinx

Xilinx Vivado Custom Part Data Files (in CVS format)

Collection of memory configuration files for Xilinx Vivado along with example design for a few boards.

Xilinx Vivado Custom Part Data Files (in CVS format)

Tested with Vivado version 2019.2 & 2022.1

DDR4 Memory

Example design for Ballistix 4GB UDIMM's

BCU1525 quad-channel example usage

Clone repo, go to your project directory and source TCL script from Vivado. For example:
cd ~
git clone https://github.com/D953i/Custom_Part_Data_Files.git

In Vivado TCL console:
source ../_github/Custom_Part_Data_Files/Boards/Xilinx_BCU1525/create_project.tcl

BCU1525 create project by using tcl script

Vivado_Source_Script

BCU1525 quad-channel ddr4 example block diagram

Vivado_Block_Diagram

BCU1525 quad-channel dd4 example memory map

Vivado_Memory_Map

BCU1525 quad-channel ddr4 example calibration

Vivado_Calibration

Useful links