-
While the [README.md](https://github.com/vortexgpgpu/vortex/blob/15ca8290d0c3cfcc559e78cec98d87172c7e6719/README.md?plain=1#L20) mentions U250 as a supported FPGA, it seems Alveo U200 is supported at …
-
Setting up the Xiling Spartan-6 involves installing a VM which is capable of running ISE 14.7.
From here we can write the firmware in VHDL if we connect the JTAG to the FPGA.
The development ar…
-
When updating a petalinux environment via `petalinux-config --get-hw-description .` I get an IndexError at your scripts in the post-process phase.
I added some smaller print statements inside the fil…
-
Hello, I was wondering how can I use ReconROS for Kria26. Are the improvement steps consistent with the ZCU102 improvement steps?
Thank you!
I read your latest paper on fpgaDDS and am very intereste…
-
Hello, I would like to reproduce the fpgaDDS on the Xilinx kria26 series development board, can you provide some implementation details.
Thank you!
-
I am developing an application using the AXI4 FIFO and started by using the axis-fifo driver included in xilinx-linux. I have found that modifications made in this repository are not in the xilinx-li…
-
There are two 'syn.cflags' defined in below two cfg files.
HLS synthesis will fail with error "ERROR: [HLS 200-1923] Found duplicate ini entry [hls] syn.cflags"
https://github.com/Xilinx/Vitis-Tut…
-
### Is there an existing CVA6 task for this?
- [X] I have searched the existing task issues
### Task Description
I have a private fork of the cva6 project in which I have added hardware and softwar…
-
Hello,
Thanks for this wonderful project.
I'm trying to deploy the Vortex GPU to Xilinx Alveo U50.
However, the IPC mismatches the results in Vortex Paper.
![paper](https://github.com/vortexgpg…
-
Hi Taichi,
Thanks for taking care of this project! I am trying to compile it with Vivado, but I have some problems with Xelab, so I need some help.
More specifically, I tried these versions and …