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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X] Yes…
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Since this depends on project x rays, and project x rays depends on an old version of vivado, I guess this project requires vivado, then?
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We are using the vivado 2019.1 linux version lab edition
[Vivado 2019.1: Lab Edition - Linux] filename=Xilinx_Vivado_Lab_Lin_2019.1_0524_1430.tar.gz)
but it has no specific VIVADO_HLS. and we g…
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I have generated file occamy_mesh_floo_noc.sv successfully and I want to make a Simulation in Vivado. File floo_narrow_wide_chimney.sv is a submodular of occamy_mesh_floo_noc.sv and it includes regist…
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A number of fuzzers (and associated minitests) work on Vivado 2017.2 but are broken on Vivado 2017.3. A quick analysis shows its related to MUXF8.
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I encountered a synthesis error while building the OpenNIC shell for the Alveo U45N board. The error message is as follows:
ERROR: [Vivado 12-13638] Failed runs(s) : 'synth_1'
'synth_1' run failed …
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There are quite a few Ethernet MAC cores, but mostly in Verilog. I've a project written in VHDL, use GHDL, and therefore looked for a core written in VHDL, and found this project.
The core was tested…
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Hi Taichi,
Thanks for taking care of this project! I am trying to compile it with Vivado, but I have some problems with Xelab, so I need some help.
More specifically, I tried these versions and …
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if using the cheby-generated AXI4-Lite interface in Vivado block design without a wrapper following issues arise:
* the naming of the interface does not follow usual scheme of `[MS]_AXI_NAME`, inst…
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Starting this issue as a tracker where we can keep our ideas and progress.
**Current conclusions**
Yosys can be extremely quick and could be added as a backend for netlist builds. These netlists m…