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Digital-EDA
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Digital-IDE
All in one vscode plugin for HDL development
MIT License
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代码跳转定义失效和代码高亮的一些加强
#82
AASWEETBOY
opened
1 week ago
0
fileset "source_1" should be "sources_1"
#81
cyrus28214
closed
1 week ago
0
wavedrom的node和edge中的字体显示都是白底,导致字体看不到
#80
wuyoutech
closed
1 month ago
0
module port附近有注释,会导致解析文档的port表格description列混乱
#78
GarenZZ
opened
1 month ago
0
模块参数注释导致自动生成的配套文档Port Name显示错误。
#77
ssl-view
opened
1 month ago
0
悬停提示识别到错误内容
#76
narutozxp
opened
3 months ago
3
Outline解析功能崩溃问题定位
#75
GarenZZ
opened
3 months ago
0
Verilog的数字语法高亮
#74
xqXQzzz1
opened
3 months ago
0
【结构树错误 二级bug】点击子模块无法跳转
#73
Nitcloud
opened
3 months ago
0
关于波形显示的一些建议
#71
lancyjk
opened
4 months ago
2
采用iverilog生成的VCD貌似无法解析仿真数据
#70
chesswei1
opened
4 months ago
1
【v0.3.2】模块调用后netlist生成错误,且仿真报错
#69
Autumeqscz
opened
4 months ago
0
网表优化与插入文档
#68
lancyjk
opened
4 months ago
1
插件文档导出问题
#67
lancyjk
closed
4 months ago
3
[0.3.3 beta] 含参数模型的例化存在问题以及拓展快捷键失效的问题
#66
light-ly
closed
4 months ago
6
【v0.3.2】testbench修改之后再次仿真会报错
#65
Autumeqscz
opened
5 months ago
1
[0.3.2] [问题] 含参数的 Verilog 模块自动例化,代码格式不正确
#64
light-ly
closed
4 months ago
1
【报错】RuntimeError: null function or function signature mismatch
#63
mathsmatics
opened
5 months ago
7
报错:verilog解析器无法解析以下代码
#62
wzw123098
opened
5 months ago
2
报错:verilog解析器的bug
#61
wzw123098
closed
5 months ago
1
功能建议-能增加点类似Verilog-Mode的功能么
#60
qinyalei
opened
5 months ago
0
报错:RuntimeError: null function or function signature mismatch、无法识别HDL文件
#55
cyl-0411
opened
6 months ago
1
Maximum call stack size exceeded
#54
412192816
opened
7 months ago
0
例化模块自动生成tb文件报错Unknown module type
#53
412192816
closed
7 months ago
1
Errors happen when parsing d:/danpj/fpga/modelsim/mod1/user/src/count4.v. Error: "RuntimeError: null function or function signature mismatch". Just propose a valuable issue in our github repo
#52
djqingwa
opened
8 months ago
1
自动例化报错
#51
zjutxzq
closed
8 months ago
3
会尝试读取gowin 的临时文件
#50
sysytwl
opened
8 months ago
1
【问题】【0.3.2】重复提示 Error: "RuntimeError: null function or function signature mismatch"
#49
Rlxzmdd
opened
8 months ago
2
【0.3.2】【问题】1无法解析localparam 2 带参数模块例化
#48
HysenEcho
opened
8 months ago
0
基础教程太少
#47
Liber1917
opened
8 months ago
5
.v源文件未被正确识别
#46
bin0612
closed
3 months ago
3
重复仿真时报错
#45
firerock1
closed
3 months ago
2
插件不能使用
#44
ZcCarvell
opened
9 months ago
2
关于netlist的生成错误
#43
s-yuan
opened
9 months ago
1
[0.3.2] 支持对verilator 的dpi-c机制的支持
#42
CzealChen
opened
9 months ago
0
[0.3.2] 离线支持+SV支持
#41
JackBlake
opened
9 months ago
1
Bad webstie connection on README
#40
LucivorLin
closed
9 months ago
1
在声明数据位宽时使用宏定义会报错
#39
Nephino
opened
9 months ago
0
0.3.2 无verilog语法检查,且提示RuntimeError
#38
LFZhou2000
closed
3 months ago
3
[0.3.2] 模块定义跳转偶尔会出现问题
#37
DreamLand7707
opened
9 months ago
1
[0.3.2] 代码补全有多个内容完全相同的选项
#36
DreamLand7707
closed
9 months ago
2
[0.3.2] 例化模块的类型,模块名称的代码高亮不变色
#35
DreamLand7707
opened
9 months ago
2
文档中的params和ports数反了
#34
jxzsxsp
closed
3 months ago
3
[建议]:优化Formatter与文档生成
#33
HysenEcho
opened
9 months ago
2
[0.3.2] Linter(vivado) 启用无效 (还是说我用的vivado2023太新了?)
#32
DuBirdFly
closed
9 months ago
1
[0.3.2]数值悬停提示不支持'_'语法
#31
DuBirdFly
opened
9 months ago
1
[0.3.2]module的#后的parameter能悬停显示数值, 但内部parameter的不能
#30
DuBirdFly
opened
9 months ago
1
[0.3.2]param语法错误会弹右下角报错弹窗, TreeView刷新按钮无效
#29
DuBirdFly
opened
9 months ago
3
0.3.0版本后存在bug,构建项目后仿真无法运行
#28
MaxWei250
opened
10 months ago
0
建议:模块例化可以基于文件夹来检索,当文件比较多时更整洁一点。
#27
MaxWei250
closed
4 months ago
1
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