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dayalannair
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FMCW_FFT_Radar
Implementation of the Xilinx FFT IP using a UART packetised data stream
MIT License
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Sawtooth FMCW Drawback
#40
dayalannair
opened
2 years ago
0
Python timing
#39
dayalannair
opened
2 years ago
1
LaTeX benign bug
#38
dayalannair
closed
2 years ago
1
Fequency estimation algorithms in industry
#37
dayalannair
opened
2 years ago
38
Simulation timing accuracy
#36
dayalannair
opened
2 years ago
12
Performance comparison
#35
dayalannair
closed
2 years ago
2
Good verilog listing style
#34
dayalannair
closed
2 years ago
11
FPGA unconnected pins
#33
dayalannair
closed
2 years ago
3
Triangle or Sawtooth modulation? (trivial but safe to ask)
#32
dayalannair
closed
2 years ago
1
MULTI SWEEP (FINAL DESIGN) WORKING
#31
dayalannair
closed
2 years ago
2
Gen Bitstream Vivado observation
#30
dayalannair
closed
2 years ago
2
Output right shifted and incorrect/missing samples around 0 Hz
#29
dayalannair
closed
2 years ago
5
Tree diagram
#28
dayalannair
closed
2 years ago
1
WORKING STREAM
#27
dayalannair
closed
2 years ago
1
Packaging data using Python
#26
dayalannair
closed
2 years ago
1
FFT hungry for DATA
#25
dayalannair
closed
2 years ago
4
Data feed slight issue
#24
dayalannair
closed
2 years ago
3
Notes on reading data in Testbench
#23
dayalannair
closed
2 years ago
8
Code submission
#22
dayalannair
opened
2 years ago
5
AXI Interface possibly working in sim
#21
dayalannair
closed
2 years ago
0
Buffer config
#20
dayalannair
closed
2 years ago
1
Send FFT data bug
#19
dayalannair
closed
2 years ago
1
FFT input stream needing too many zero pads
#18
dayalannair
closed
2 years ago
9
Simulation timescale
#17
dayalannair
closed
2 years ago
1
FFT strange behaviour
#16
dayalannair
closed
2 years ago
2
FIFO vs. Buffer
#15
dayalannair
closed
2 years ago
2
Last sample = First sample = Large number
#14
dayalannair
closed
2 years ago
2
Future work/possible additions
#13
dayalannair
closed
2 years ago
2
Report
#12
dayalannair
closed
2 years ago
0
WORKING!
#11
dayalannair
closed
2 years ago
13
Comparator performance in Verilog
#10
dayalannair
closed
2 years ago
12
FIFO missed first FFT output sample
#9
dayalannair
closed
2 years ago
9
Python script
#8
dayalannair
closed
2 years ago
14
FIFO
#7
dayalannair
closed
2 years ago
3
Data transfer methods
#6
dayalannair
closed
2 years ago
2
FFT Fixed - is method suitable?
#5
dayalannair
closed
2 years ago
2
Noise in real data
#4
dayalannair
closed
2 years ago
3
FFT Improvements
#3
dayalannair
closed
2 years ago
8
FFT IP Incorrect results
#2
dayalannair
closed
2 years ago
25
FFT accepting more data than specified
#1
dayalannair
closed
2 years ago
6