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devanshi-jain / max_finder

Implementation of Automatic Gain Control with four different gain loops using an RTL level simulation is performed. The design is carried out using the systemVerilog HDL (Hardware Description Language). The resulting hardware design is compiled to fit into the FPGA hardware device : XC7Z010-1CLG400C.
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debug #1 #2

Open devanshi-jain opened 2 years ago

devanshi-jain commented 2 years ago

sequential logic calls for non-blocking assignment, thus, lines 81 and 82 need to rectifies accordingly.

devanshi-jain commented 2 years ago

asynchronous logic (when you have a second parameter of negedge of say, restn, at always_ff)

let's keep using synchronous since that's confirming with the rest of the database