devanshi-jain / max_finder

Implementation of Automatic Gain Control with four different gain loops using an RTL level simulation is performed. The design is carried out using the systemVerilog HDL (Hardware Description Language). The resulting hardware design is compiled to fit into the FPGA hardware device : XC7Z010-1CLG400C.

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max_finder

Implementation of Automatic Gain Control with four different gain loops using RTL. The design is carried out using the systemVerilog HDL (Hardware Description Language). The resulting hardware design is synthesized to fit into the FPGA hardware device : XC7Z010-1CLG400C.