Simulation : no drops when it reached sampling rate (500,000) indicating overflow channel does not function properly

devanshi-jain / max_finder

Implementation of Automatic Gain Control with four different gain loops using an RTL level simulation is performed. The design is carried out using the systemVerilog HDL (Hardware Description Language). The resulting hardware design is compiled to fit into the FPGA hardware device : XC7Z010-1CLG400C.

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Simulation : no drops when it reached sampling rate (500,000) indicating overflow channel does not function properly #4

Open devanshi-jain opened 2 years ago

devanshi-jain commented 2 years ago

Screenshot from 2022-05-02 10-01-12

devanshi-jain commented 2 years ago

Even tho TVALID = 1, s_axis_tvalid is not setting up properly

Screenshot from 2022-05-02 19-47-56

devanshi-jain commented 2 years ago

Screenshot from 2022-05-03 00-02-40 Fixed the tvalid issue thanks to Donovan. BUG: the max_finder module was outputting intoi s_axis_valid, thus, there being conflicting drivers (1 from testbench and a 0 from the module) causing it to be undefined.