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devanshi-jain / max_finder

Implementation of Automatic Gain Control with four different gain loops using an RTL level simulation is performed. The design is carried out using the systemVerilog HDL (Hardware Description Language). The resulting hardware design is compiled to fit into the FPGA hardware device : XC7Z010-1CLG400C.
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testbench #5

Open devanshi-jain opened 2 years ago

devanshi-jain commented 2 years ago

Is there a need to specify the number of transmit and receive ports?

devanshi-jain commented 2 years ago

Z - stands for high impedance : for multiple different drivers, no current flowing in and out of the node, has no effect to the wire