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dmolinagarcia
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74HCT6526
74HCT6526
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Second byte MSB leaks into First byte LSB on SDR dual send.
#36
dmolinagarcia
opened
9 months ago
0
U1 B3 SDR Interrupt bit clear
#35
dmolinagarcia
closed
9 months ago
3
Reduce footprint
#34
dmolinagarcia
opened
11 months ago
0
TOD IRQ should be edge-triggered
#33
dmolinagarcia
closed
11 months ago
1
ICR1 is missing
#32
dmolinagarcia
closed
11 months ago
2
TOD invalid counts
#31
dmolinagarcia
opened
12 months ago
0
TOD spurious ticks
#30
dmolinagarcia
opened
12 months ago
1
SDR receive issues
#29
dmolinagarcia
closed
9 months ago
4
SDR sends fails
#28
dmolinagarcia
closed
9 months ago
6
TOD is not setting ICR2
#27
dmolinagarcia
closed
11 months ago
5
TOD AM/PM flag is not wired properly.
#26
dmolinagarcia
closed
11 months ago
1
TOD Count is (wrongly) Enabled by default
#25
dmolinagarcia
closed
11 months ago
2
Timer Pulses are offseted half a cycle
#15
dmolinagarcia
opened
1 year ago
0
Segregate CNT edge detector
#14
dmolinagarcia
opened
1 year ago
0
02CIATIMERS
#12
dmolinagarcia
closed
1 year ago
15
IRQ clears too late
#11
dmolinagarcia
closed
1 year ago
3
TIMERA/TIMERB underflows issue.
#10
dmolinagarcia
closed
1 year ago
11
TOD implementation.
#9
dmolinagarcia
closed
1 year ago
1
Check if pdf are updated for schematic
#8
dmolinagarcia
closed
1 year ago
1
Check footpages for all schematics
#7
dmolinagarcia
closed
1 year ago
1
Should /pc be open collector?
#6
dmolinagarcia
closed
1 year ago
1
SDR clears?
#5
dmolinagarcia
opened
2 years ago
0
Timer B bug is replicated to other IRQ sources
#4
dmolinagarcia
opened
2 years ago
3
ICR
#3
dmolinagarcia
closed
1 year ago
1
// PA/PB inputs are latched on posedge of PHI2 and can then be read at negedge. Observable as a 1/2 cycle input delay.
#2
dmolinagarcia
opened
2 years ago
0