search

dpiegdon / verilog-buildingblocks

Library of generic verilog buildingblocks
GNU Lesser General Public License v3.0
16 stars 6 forks source link

Reset signal in LSFR #3

Closed DurandA closed 4 years ago

DurandA commented 4 years ago

Hi @dpiegdon!

While reading your code, I noticed than the LFSR has a strange reset condition: https://github.com/dpiegdon/verilog-buildingblocks/blob/c117298d477e3a3aa424872090b4e8a75d30fa7f/lfsr.v#L36

Shouldn't the condition be if(init_done && ~rst)?

dpiegdon commented 4 years ago

you are absolutely right. besides that, the testbench does not work either.

dpiegdon commented 4 years ago

ok, should be fixed now. please take a look, and thanks again!

DurandA commented 4 years ago

@dpiegdon May I ask a Verilog question?

How is evaluated (^(shiftreg & FEEDBACK))? This is taken from https://github.com/dpiegdon/verilog-buildingblocks/blob/a5c0dc5d70020c17ef64906e39e28a8aee27b0ed/lfsr.v#L33

Wouldn't (shiftreg ^ FEEDBACK) be equivalent to the above statement?

dpiegdon commented 4 years ago

of course! given an N-bit wide signal shiftreg, and an N-bit wide constant FEEDBACK, (shiftreg ^ FEEDBACK) resolves to an N-bit wide result that with each bit result[i] = shiftreg[i] ^ FEEDBACK[i] for i in 0..N-1. meanwhile, the prefix-version of XOR, i.e. ^signal, applies the XOR operation to each bit successively. i.e. ^signal == xor(signal[0], xor(signal[1], xor(signal[2], ...))). so in the end, the result is a single bit where each bit of signal was xor'ed together. with ^(shiftreg & FEEDBACK), this yields the xor of all bits of the feedback mask in shiftreg.

dpiegdon commented 4 years ago

(edit: pressed the 'comment' button a bit early)

DurandA commented 4 years ago

Thank you very much for the clarification. I wasn't even aware that these reduction operators existed in standard Verilog.