dpiegdon / verilog-buildingblocks

Library of generic verilog buildingblocks
GNU Lesser General Public License v3.0
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Various verilog modules that I use or develop

Contains

Contains also testbenches (*_tb.v) for some of the modules, see below.

Note: most of the implementation-specific modules should be easily adaptable to other platforms.

Testbenches

Some of the modules have a testbench (*_tb.v). Testbenches are optimizes for use with the Icarus Verilog compiler. To run all tests, just run make. The build is successfull if and only if all testbenches were able to build and succeeded.

Authors

All files except uart.v:

uart.v:

Licensing

License exceptions:

uart.v -- MIT license, see header of file.

All OTHER contained files are licensed under the LGPL v3.0, see LICENSE.txt . That means that you may use the provided verilog modules in a proprietary software without publishing your proprietary code. But you must publish any changes that you did to the provided verilog modules.

I suggest that you include this repository as a submodule. That way you can easily publish any changes separately from your own code.