Step2: Generating 72 bit number from 8 bit input (data)

[csuwalaka]

How 8 bit input can be concatenated to 72 bit at interface? Will nine 8 bit inputs need to be stored in temporary registers and then they will be concatenated to make 72 bit number or they are 9 channels each having 8 bits instead of one input of 8 bits and will be concatenated together to make 72 bit number?

[csuwalaka]

@jahagirdar

[jahagirdar]

It is a single input, single output with intermediate storage ckt.

The circuit for such conversion is called gearbox.

[csuwalaka]

In the latest revision of https://github.com/dyumnin/NCG_Interview the datawidth is shown updated to 64 bits instead of 72 bits. Regarding Gearbox circuit with the context of our design, is it like: when enable = 1 then it'll take 8 bit input, store them in temporary registers. When we get total 64 bit equivalent (like 64 bit FIFO full) then generate ready output signal so that the other device be ready to accept this 64 bit data?

[csuwalaka]

something like this: [(https://github.com/hanw/sonic-lite/blob/master/hw/verilog/gearbox/sonic_gearbox_40_66.sv)]

[jahagirdar]

Correct, Once the full 64 bits are available a req-ready assertion cycle will transfer it to the next stage.

[csuwalaka]

Okay. I'll add this assertion with the required RTL code. As in the problem statement we don't have req signal to access the output from the gearbox interface for step2 module 1, so for now there is only "ready signal equal to 1" to inform when the 72 bit output is ready to write to the bus. Should I implement req signal for requesting the data as well?

[jahagirdar]

A request + Ready protocol takes care of all corner cases. A Request only protocol indicates the destination is always ready to consume data and, A Ready only protocol indicates the source is always ready to provide data.