Take home coding test.
Assumption
Instructions:
Write a verilog module which
Has a simple interface (enable(input),ready(output) data(input)) On one end which takes in 8 bit numbers, concats them to generate a 64 bit number and writes this result to the ddr4 axi interface generated in step 1. and increments the address.
Write another module which has an interface of (enable, ready, address(in), data(out)) and interfaces to the same DDR logic in Step 1. and returns the data in DDR for the specified address.
Checkin the files and tag it as Step2
Checkin the testplan for the dut containing logic in step1 and step2 and tag it as Step3
Ref: https://verificationacademy.com/cookbook/coverage
Implement the verification env and write and verify atleast 2 test(should contain a ddr write and read). If you know python, then you can do the verification using cocotb (We use cocotb internally for all our verification).
Ref: https://cocotb.readthedocs.io/
Create a pull request on the original repo with your code submission.
Once the pull request is created we will schedule the next round of interview.
In case of any issues, raise an issue in the github issue tracking system for this repo..