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dyumnin / NCG_Interview

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Step2: Clocks #3

Open csuwalaka opened 3 years ago

csuwalaka commented 3 years ago

Are both interfaces are insensitive to clock input? If yes, then with respect to what reset will be synchronised? means will I have to make this as clock less design for both interfaces?

csuwalaka commented 3 years ago

@jahagirdar

jahagirdar commented 3 years ago

Typically DDR clock will be different from system clock, If the IP generator does not handle reset synchronization, A bit synchronizer can be used to ensure asynchronous assertion, synchronous deassertion of reset.

csuwalaka commented 3 years ago

Okay. Looking at DDR4 PHY interface IP (DFI) pin diagram, there are following reset pins:

  1. c0_ddr4_aresetn
  2. c0_ddr4_ui_clk_sync_rst
  3. At C0_DDR4, c0_ddr4_reset_n

Among the above three, which one is to be connected to reset signal in step 2 is yet to be discovered (Have to check Xilinx AXI reference guide to know more about all these pins in the DFI)?

jahagirdar commented 3 years ago

Hi, Is this issue resolved? i.e. did you check the Xilinx document and get the required information?