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dyumnin / NCG_Interview

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Step2: unstated use of clock #4

Open csuwalaka opened 3 years ago

csuwalaka commented 3 years ago

In step2, address need to be incremented. If there is no synchronous element like clock then address = address + 1 will generate a combinational loop. Also, the gearbox circuit used as user interface in this step must be sequential circuit to change the state to get total 64 bit data at the output. This means step 2 should have clock input which is not mentioned on the specification page.

jahagirdar commented 3 years ago

You can use the axi clock as the default system clock.

csuwalaka commented 3 years ago

Okay. But I observed that with respect to #3 [https://github.com/dyumnin/NCG_Interview/issues/3#issuecomment-734801784], Vivado IP generator is able to generate c0_ddr4_ui_clk_sync_rst signal (DDR4 reset) and c0_ddr4_ui_clk (DDR4 clock) in addition to sys_rst (system reset) and c0_sys_clk (system clock). So, looks like I should use them (DDR4 clock and reset signals) as default clock and reset signals instead of system clock and reset signals. Is it correct?

jahagirdar commented 3 years ago

Xilinx PG 150 app note has clocking and other interfacing related information.