efabless / caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
https://caravel-harness.readthedocs.io/
Apache License 2.0
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LVS/CVC issues with caravel modules #41

Open d-m-bailey opened 3 years ago

d-m-bailey commented 3 years ago

This issue is an on going list of the device level LVS and CVC issues with caravel modules. origin/develop commit 384a7d517a82c49a0c4411c8132ce3f97eebfad5 magic 8.3.133 The indentation of the list is intended to show the hierachy. Unless otherwise indicated, CVC was run on the netlist extracted from GDS.

Cell LVS CVC
caravel
+ chip_io
+ gpio_control_block OK? (vssd matched to vssd1) OK
+ mgmt_core OK OK
| + DFFRAM OK OK
| - digital_pll OK OK
+ mgmt_protect - OK
| + mgmt_protect_hv NG (verilog missing decap) -
| + mprj2_logic_high OK -
| - mprj_logic_high OK -
+ simple_por NG (verilog and gds contain different cells)
+ sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped NG (library spice incorrect) OK
+ storage NG (bus index mapping incorrect) NG (Hi-Z inputs)
| - sram_1rw1r_32_256_8_sky130 - -
+ user_id_programming OK OK
+ user_project_wrapper OK OK
| - user_proj_example OK -
ax3ghazy commented 3 years ago

@d-m-bailey: Thanks!

I have renamed the old device names to the new sky130 equivalents in the SRAM spice netlist we got from OpenRAM. Please check if this helps: https://github.com/efabless/sky130_sram_macros/blob/sky130_name_mapping/sram_1rw1r_32_256_8_sky130/sram_1rw1r_32_256_8_sky130.lvs.converted.sp

d-m-bailey commented 3 years ago

For running device level LVS and CVC on other projects on the MPW (assuming user_project_wrapper is the only difference).

  1. cd project
  2. Uncompress gds/user_project_wrapper.gds
  3. Recursively check for referenced modules in verilog/gl/user_project_wrapper.v awk '/ \(/ {print $1}' verilog/gl/user_project_wrapper.v | sort -u | grep -v sky130_fd_sc_hd__
  4. For each submodule detected in 2, add an entry in openlane/user_project_wrapper/config.tcl
    set ::env(LVS_EXTRA_GATE_LEVEL_VERILOG) "
    $script_dir/../../verilog/gl/submodule1.v
    $script_dir/../../verilog/gl/submodule2.v
    ..."
  5. From docker, in project/openlane extract device level spice from layout.
    flow.tcl -design user_project_wrapper -tag lvs -lvs -net ../verilog/gl/user_project_wrapper.v -gds ../gds/user_project_wrapper.gds
  6. Create spi2cdl script
    
    cat > spi2cdl <<'!'
    # /bin/bash

mkdir -p $1/runs/lvs/results/cvc

awk ' /^X. .pr[^ ]fet.=/ { print "M" $0; next;
} /^X.*pr
diode/ { print "D" $0; next;
} /^X.pr__cap_mimm3. / { print "C" $0; next;
} /^X.
prres_xhigh_po / { $4 = ""; print "R" $0; next;
} /^X.*pr
resgeneric.d/ { $6 = sprintf("$SUB=%s %s", $4, $6); $4 = ""; print "R" $0; next;
} { print $0; } ' $1/runs/lvs/results/magic/$1.gds.spice > $1/runs/lvs/results/cvc/$1.cdl !