efabless / caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
https://caravel-harness.readthedocs.io/
Apache License 2.0
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caravel magic openram openroad picorv32 sky130 yosys

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Caravel Harness

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Table of contents

Overview

Caravel is a template SoC for Google SKY130 free shuttles. The current SoC architecture is given below.

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Datasheet and detailed documentation exist here <https://caravel-harness.readthedocs.io/>__

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.. _getting-started:

Caravel Architecture

Caravel is composed of three main sub-blocks: management area, storage area, and user project area.

.. _management-area:

Management Area

The managment area includes a picorv32 <https://github.com/cliffordwolf/picorv32>__ based SoC that includes a number of periphrals like timers, uart, and gpio. The managemnt area runs firmware that can be used to:

For a complete list of the SoC periphrals, check the memory map <https://github.com/efabless/caravel/blob/master/verilog/rtl/README>__

.. _storage-area:

Storage Area

The storage area is an auxiliary storage space for the managment SoC. It holds two dual port RAM blocks (1KB) generated by OpenRAM <https://github.com/VLSIDA/OpenRAM.git>__

The storage area is only accessible by the management SoC.

.. _user-project-area:

User Project Area

This is the user space. It has a limited silicon area 2.92mm x 3.52mm as well as a fixed number of I/O pads 38 and power pads 4.

The user space has access to the following utilities provided by the management SoC:

Quick Start for User Projects

Your area is the full user space, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper for digital projects or insert it into user_project_analog_wrapper for analog projects.

.. _digital-user-project:

Digital User Project

If you are building a digital project for the user space, check a sample project at caravel_user_project <https://github.com/efabless/caravel_user_project>__.

If you will use OpenLANE to harden your design, go through the instructions in this README <https://github.com/efabless/caravel/blob/master/openlane/README.rst>__.

Digital user projects should adhere the following requirements:

.. _analog-user-project:

Analog User Project

If you are building an analog project for the user space, check a sample project at caravel_user_project_analog <https://github.com/efabless/caravel_user_project_analog>__.

Analog user projects should adhere the following requirements:


IMPORTANT ^^^^^^^^^

Please make sure to run make compress before commiting anything to your repository. Avoid having 2 versions of the gds/user_project_wrapper.gds one compressed and the other not compressed.

For information on tooling and versioning, please refer to tool-versioning.rst <./docs/source/tool-versioning.rst>__.


Required Directory Structure

NOTE:

If you're using openlane to harden your design, the ``verilog/gl`` ``def/`` ``lef/`` ``gds/`` ``mag`` ``maglef`` directories should
be automatically populated by openlane.

.. _additional-material:

Additional Material

.. _mpw-two:

MPW Two

.. _mpw-one:

MPW One

Check mpw-one-final <https://github.com/efabless/caravel/tree/mpw-one-final>__ for the caravel used for the mpw-one tapeout.

:warning: You don't need to integrate your design with Caravel GDS for MPW two. Running make ship is no longer required.

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