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Implementation of OpenRAM to utilize the memory provided by OpenRAM, this will cause some changes in the Fetch part (IFU) and Load Store Unit (LSU).
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**Describe the bug**
_Some_ pins are not connected to the routing grid. In more detail, sometimes zero, one, or two intermediate pins are not connected.
Could be user error.
**Version**
OpenRAM…
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In OpenRAM when creating an SRAM with the following configuration
```word_size = 16
num_words = 256
words_per_row = 1
tech_name = "sky130"
num_banks = 2
num_rw_ports = 1
num_r_ports = 0
nu…
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Hello,
I'm trying to re-run the generation steps here as a way to learn more about OpenRAM with sky130. I'm using the main branch of [OpenRAM](https://github.com/VLSIDA/OpenRAM), but this appears…
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This feedback is for : https://armleo-openlane.readthedocs.io/en/merge-window-4/docs/source/openram.html
1. Simplify intro to:
This guide covers the RTL-to-GDS flow using OpenRAM cells and many m…
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**Describe the bug**
I ran the sky130_sram_1rw_tiny example and the power report shows hundreds of watts, which seems wrong. Could this be a bug? How can I solve it?
![image](https://github.com/VLSI…
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### Description
Following a tutorial I got an error in interactive mode. Any step of a tutorial which requires an interactive mode do not work.
### Expected Behavior
On the command
```
or_gu…
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The read_celllib command reads a cell library, but it does not recognize memories. These require support for busses and the memory cell type. You can see an example from OpenRAM at:
https://github.…
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I am encountering LVS mismatch issues while generating a single-port SRAM using the Sky130 technology.
Could the problem be related to num_spare_col and num_spare_row in our config? How can I address…
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### Description
Hello everyone, I am trying to implement SRAM macros inside caravel user area. Everything works fine until DRC step. In the DRC step, I get this error message.
```
[ERROR]: during e…