efabless sky130_sram_macros_old issues - Githubissues

efabless / sky130_sram_macros_old

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Set VERBOSE = 0

#12 antonblanchard closed 2 years ago
3
Set VERBOSE = 0

#11 antonblanchard closed 2 years ago
1
Generated macros uses analytical model rather than spice simulation

#10 mithro opened 2 years ago
1
Very small max_transition

#9 maliberty opened 2 years ago
6
Verilog syntax error?

#8 nayiri-k closed 3 years ago
3
Liberty Files

#7 nayiri-k closed 3 years ago
2
sky130_sram_* modules pins sizes changed to be slightly > 0.24

#6 ahmednofal closed 3 years ago
7
Fixed simultaneous reading and writing behavior.

#5 milovanovic closed 3 years ago
0
Add initial FuseSoC core description file

#4 olofk closed 3 years ago
1
VLNV identifier

#3 olofk opened 3 years ago
2
OpenRAM branch to use

#2 mballance opened 3 years ago
2
sram_1rw1r_32_256_8_sky130 model mismatches

#1 20Mhz closed 3 years ago
4