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Are any of the following open-source CPUs targets for powdr?
Specifically, should I ever expect that powdr will run on, say, the Berkeley/SiFive Rocket [rv32ima](https://github.com/chipsalliance/ro…
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I have modified the Pico RISC-V core with crypto algorithms and want to get updated Fmax. Is there any way to calculate the latency introduced without running on FPGA using any example or test in simu…
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Hello! I've still got my BlackIce-II board and am trying to get Clifford Wolf's PicoRV32 running on it. I'm running into some problems with getting next-pnr to create an "hx4k" pathway (I know that th…
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This file is large and copied in a bunch of places. Make a central location and reference it from our projects
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Hi All,
I am after a HLT (HALT) kind of wait function and was happy to find the "picorv32_waitirq_insn" function. However, I am not sure I understand what the attended behavior should be. In the P…
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Unfortunately, it seems like this core does not drop cleanly into the latest version of Vivado.
Here is the error output when trying to add to a block design:
```
create_bd_cell -type ip -vlnv cl…
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Hello.
hdlConvertor does not support the parallel_case attribute. An example can be found here: https://github.com/KatCe/hdlConvertor_issue_185
Using the python script in the repo I tried all 3…
KatCe updated
11 months ago
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I have added a 8 bit wishbone peripheral as follows:
```
class SpiModule(Module):
def __init__(self, platform, spi_miso, spi_mosi, spi_ss_n, spi_sclk):
self.bus = bus = wishbone.…
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Hi, can any one tell me how to access the example pcpi instruction "picorv32_pcpi_mul" from the software. Can I access it using the asm function in c?
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Hello,
I've a lot of issues with the SRAM example with the io constraints like `sram_addr_to_pad` not known.
When I try to change it to `ADR` in the file `sram_io_ice40`, I've got an error:
`ch…