Nic30 hdlConvertor issues

Nic30 / hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

MIT License

274 stars 63 forks source link

issues

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Error in CMake based build

#190 Siddhartha123 opened 1 month ago
2
VHDL components are incorectly rewritten from HDL AST back to VHDL

#189 Jenkins047 closed 2 months ago
0
GitHub CI with Prebuilt Binary Wheel

#188 khwong-c closed 5 months ago
5
Prebuilt Binary Release to PyPi

#187 khwong-c opened 5 months ago
9
tests+verilog preproc: Fix ANTLR <=4.9, CMake and Icarus tests

#186 kleinesfilmroellchen closed 5 months ago
5
(System)Verilog parallel_case attribute is not supported

#185 KatCe opened 8 months ago
1
Dockerfile is outdated

#184 KatCe closed 5 months ago
4
Can't build master on ubuntu 22.04

#183 poleguy closed 5 months ago
6
CMake install DIRECTORY include wrong parameters?

#182 liuzikai opened 1 year ago
2
fix: PythonLibs issue

#181 henryiii closed 5 months ago
1
Error when preprocessing verilog header with dos line endings

#180 nxpMartin closed 5 months ago
5
Build error on windows

#179 TitanCheat closed 1 year ago
2
Using updated SV/Verilog, VHDL Grammars

#178 AmeyaVS opened 1 year ago
2
Updating Git Submodules For Tests

#177 AmeyaVS opened 1 year ago
1
Initial Version to fix Verilog Primitive Structural Code(Fixes #173)

#176 AmeyaVS closed 1 year ago
5
Debug Build Documentation Update

#175 AmeyaVS closed 1 year ago
3
Fix Antlr4.10 std::any usage

#174 AmeyaVS closed 1 year ago
3
`Conversion to Python object not implemented` Error from Primitive Structural Verilog Code

#173 TheMatt2 closed 1 year ago
3
provided instructions don't work for finding antlr-complete.jar

#172 bsferrazza closed 1 year ago
6
ANTLR 4.11.1 support

#171 apatern0 closed 1 year ago
2
KeyError when working with ternary operators and ranges?

#170 shafe123 closed 1 year ago
3
Verilog2017 - unpacked array converted as packed

#169 diffore opened 2 years ago
2
Convert VHDL package to Verilog or SV

#168 jabate-anova opened 2 years ago
2
Add sv2chisel in related projects

#167 johnsbrew closed 2 years ago
1
incorrect Position

#166 Thomasb81 opened 2 years ago
5
Preprocessor - expose complete parser?

#165 the-moog opened 2 years ago
11
Question regarding VHDL to hwt

#164 kaidoho closed 1 year ago
4
Handling extraneous commas (SystemVerilog)

#163 the-moog opened 2 years ago
1
Replace scikit-build/cmake with mesonpep517/meson (potential drop of python2.7 support)

#162 Nic30 opened 2 years ago
1
Added some support for Block statement

#161 hdl4fpga closed 2 years ago
2
SV grammar hirarchical identifier in delay_value rule

#160 Thomasb81 opened 2 years ago
0
Test std2017_p333 has incorrect syntax

#159 jrudess closed 2 years ago
1
Shared Variables within VHDL not implemented?

#158 hjnauman closed 3 years ago
7
Value attribute missing from HdlIdDef objects when declared on the same line.

#157 hjnauman closed 3 years ago
1
Added tests for VHDL issues (#152 #153 #154 #155)

#156 Partidani closed 3 years ago
3
VHDL: Functions with no arguments are not handled correctly when trying to write AST to VHDL

#155 Partidani closed 3 years ago
4
VHDL: open is not handled correctly when trying to write AST to VHDL

#154 Partidani closed 3 years ago
1
VHDL: direct instantiation is not handled correctly when trying to write AST to VHDL

#153 Partidani closed 3 years ago
1
VHDL: exit statements are not handled in the HDL AST

#152 Partidani closed 3 years ago
1
NotImplementedError: Unexpected object of type Error,

#151 SingaDK closed 3 years ago
4
Added a quick txt file with some instillation and build help for Windows

#150 hjnauman closed 3 years ago
1
SystemVerilog import package - doesn't seem to do anything?

#149 flemish4 opened 3 years ago
8
VHDL: proper tests for comment parsing

#148 Nic30 opened 3 years ago
0
VHDL: cannot visit NULL statement

#147 andrasm62 closed 3 years ago
2
VHDL: cannot visit FOR LOOP within a function

#146 andrasm62 closed 3 years ago
5
Fix syntax error

#145 dalance closed 3 years ago
2
Can the normal mode and the preprocessing mode SystemVerilog Grammar be combined into one file?

#144 itviewer closed 3 years ago
5
Visual Studio 2019 x64 exit code -1073741571 (probably memory leak)

#143 Nic30 closed 3 years ago
1
Fix minor test errors

#142 wsnyder closed 3 years ago
1
VHDL: Arrays of unbounded elements not working correctly.

#141 mewais opened 3 years ago
0