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I mentioned this to @cknizek -- he may take a crack at it.
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Starting this issue as a tracker where we can keep our ideas and progress.
**Current conclusions**
Yosys can be extremely quick and could be added as a backend for netlist builds. These netlists m…
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README states:
> This build is aggressively optimized for binary size and startup latency, and only includes features required by Amaranth's Verilog and CXXRTL backends; it is not useful for any ot…
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**Description**
When using the GHDL plugin to yosys, and probably more generally, attributes are not attached to instantiations. This causes (for example) yosys to optimise away instantiated blocks …
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TerosHDL:Global output: 2024-06-19 09:53:02.780 [info] [00000.001204] ERROR: Can't guess frontend for input file `d:/workSpace/sim/fifo/axis_async_fifo.v;' (missing -f option)!
When I'm in the CMD wi…
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yosys -m ghdl -p "ghdl --std=93c --ieee=synopsys -fexplicit -Whide -Wspecs dut2; write_cxxrtl blink.cpp"
/----------------------------------------------------------------------------\
| yosys -…
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### Version
Yosys 0.39+165
### On which OS did this happen?
Linux
### Reproduction Steps
Consider the following code:
`y2` has a bit width of `3` bits, and when it is `3'b111`, the value of `y`…
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### Version
The 0.42 tarball (can't build, so can't give yosys --version otuput)
### On which OS did this happen?
Linux
### Reproduction Steps
```
tar -xzf yosys-yosys-0.42.tar.gz
cd yosys-yosy…
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I know that UHDM can be imported into Yosys AST, and after Yosys performs synthesis, it can generate an SMT2 file. But for some formal verification apps, synthesis is unnecessary, and importing into Y…
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**Describe the bug**
When I click to the Schematic viewer button, the out put is :
2024-03-11 12:53:09.710 [error] Yosys failed.
2024-03-11 12:53:09.716 [info] yowasp-yosys -p "read_verilog -sv …