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efeslab
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hardware-bugbase
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fix: fix pc-dependent configurations in makefile
#11
JacyCui
closed
5 months ago
2
A possible bug about the verilator reproducing Makefile
#10
JacyCui
closed
5 months ago
4
fix: d12 readme typos
#9
yihuajack
closed
2 years ago
0
Adding a new bug repo -- verilog-axis
#8
HieronZhang
closed
3 years ago
0
Synthesize and perform depth-sweep on all xilinx bugs
#7
Alkaid-Benetnash
closed
3 years ago
0
Use debugging helper passes on all HARP bugs
#6
Alkaid-Benetnash
closed
3 years ago
0
Manual bug study
#5
Alkaid-Benetnash
closed
3 years ago
0
Synthesize the AXI-lite (after verilator) in vivado.
#4
Alkaid-Benetnash
closed
3 years ago
0
Add scripts for signaltap resource utilization experiments
#3
Alkaid-Benetnash
closed
3 years ago
0
Add a shared "synth" make target to synthesize instrumented HARP-based applications
#2
Alkaid-Benetnash
closed
3 years ago
0
Annotate debugging-related display tasks with "debug_display" verilator tag for HARP-based applications
#1
Alkaid-Benetnash
closed
3 years ago
0