This repository is a playground for exploring and comparing how configuration is handled by different tools for development of (V)HDL projects. The main motivation is hopefully finding a universal format/procedure for reducing duplication. The repository is organised as follows:
constraints (hdl/constraints): board constraint files (*.lpf, *.pcf, etc.), which can be reused by multiple designs.prog: each subdir contains helper resources for a different programming tool, which can be reused by multiple designs.modules: each subdir contains a different design and the corresponding specific sources for each of the tested tools.
demo: basic design with a counter for making a LED blink and an UART loopback (hard-wire), based on antonblanchard/ghdl-yosys-blink: vhdl_blink.vhdl.leds: single entity and multiple architectures for generating patterns with 5 LEDs, based on ghdl/ghdl-yosys-plugin: examples/icestick/leds.full_adder: full adder example from GHDL's Quick Start Guide (Full adder module and testbench)uart: UART sender and receiver, based on ghdl/ghdl-yosys-plugin: examples/icestick/uart.GHDLSynth: naive adaptation of the Makefiles from ghdl/ghdl-yosys-plugin to a Python class.The following table shows which tool examples were contributed to this repository already. Some of them are used in some modules only (yet).
| demo | leds | full_adder | uart | |
|---|---|---|---|---|
| GHDLSynth | Yes *1 | |||
| VUnit | Yes | |||
| pyFPGA | Yes *2 | |||
Not all the modules were used in all the boards yet. The following list shows the combinations that are known to work:
leds/src/leds.vhdl leds/src/$arch | for arch in blink fixed multi1 multi2 rotate1 rotate2 rotate3 rotate4 spinuart/src/uart_tx.vhd uart/src/uart_tx.vhd uart/src/uart_top.vhddemo/src/demo.vhd