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enjoy-digital
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litepcie
Small footprint and configurable PCIe core
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Issues with UltraScale+ PCIe IP naming
#39
daveshah1
closed
4 years ago
5
Queries about litepcie
#38
imBilal1998
closed
3 years ago
4
Feedback / Contribution / Support
#37
enjoy-digital
opened
4 years ago
0
Check PCIe bus rescan after loading bitstream.
#36
enjoy-digital
opened
4 years ago
5
Create /dev/ttyX device on Host to access crossover UART when kernel driver is loaded
#35
enjoy-digital
opened
4 years ago
5
Allow MMAP access to BAR0 without loading kernel driver
#34
enjoy-digital
closed
3 years ago
5
Kernel driver improvements
#33
sergachev
closed
2 years ago
6
example: fix phy type
#32
sergachev
closed
4 years ago
1
Re-integrate driver improvements in new version of the driver
#31
enjoy-digital
closed
2 years ago
3
New driver
#30
enjoy-digital
closed
4 years ago
0
kernel: remove unnecessary call to pci_release_regions() on device remove
#29
sergachev
closed
4 years ago
1
test_dma: remove unused imports and variables, fix mistypes
#28
sergachev
closed
4 years ago
1
dma: fix mistypes in comments
#27
sergachev
closed
4 years ago
1
Fix kernel module unloading
#26
gbip
closed
4 years ago
10
software: fix definitions
#25
sergachev
closed
4 years ago
1
Improve kernel driver
#24
sergachev
closed
4 years ago
1
software: include cdev.h
#23
sergachev
closed
4 years ago
1
replace printk with appropriate functions: dev_err, pr_err etc; remove unnecessary malloc error print
#22
sergachev
closed
4 years ago
1
add pyyaml to setup.py
#21
sergachev
closed
4 years ago
1
Support LitePCIe on Lattice ECP5 SERDES (with open toolchain)
#20
mithro
closed
3 years ago
12
Support for Altera
#19
vbuitvydas
closed
5 years ago
1
Example Design
#18
shahbaazlokh
closed
5 years ago
1
Segmentation fault when running litepcie_util dma_loopback_test
#17
nanortemis
closed
5 years ago
4
Linux kernel space software does not compile
#16
nanortemis
closed
5 years ago
1
Linux user space software does not compile
#15
nanortemis
closed
5 years ago
1
Possible roadmap for the project for PCIE Gen3?
#14
anmolsahoo25
closed
5 years ago
6
refactor/simplify reordering
#13
enjoy-digital
closed
5 years ago
0
License on the PCIE Verilog files?
#12
anmolsahoo25
closed
5 years ago
1
Add Power9 support
#11
enjoy-digital
closed
3 years ago
13
Link not stable with some Ivy Bridge Xeon in Gen2 X2/X4
#10
enjoy-digital
closed
5 years ago
1
Is there anyway to specify the install dir of the FPGA tools?
#9
ShawnLess
closed
6 years ago
5
conflict IRQ
#8
ShawnLess
closed
6 years ago
3
Fix all remaining indentation issues in python code
#7
felixheld
closed
6 years ago
0
fix code indentation
#6
felixheld
closed
6 years ago
1
Add 128 bits support (will allow PCIe Gen2 X4 on Artix7)
#5
enjoy-digital
closed
6 years ago
1
Adding .gitignore.
#4
mithro
closed
6 years ago
0
Interrupt vector conflict for IRQ 0
#3
ghost
closed
6 years ago
1
Confused on setup.
#2
omstation
closed
6 years ago
5
adapt simulations to new simulator
#1
enjoy-digital
closed
8 years ago
2
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