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enjoy-digital / litesata

Small footprint and configurable SATA core
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Switch PHYs to LiteICLink #19

Closed enjoy-digital closed 3 years ago

enjoy-digital commented 3 years ago

LiteICLink simplifies the use of transceivers with FPGAs and is already used by others cores to handle the lower layers(for example in LiteJESD204B and with the USB3 PIPE). LiteSATA was created before LiteICLink, so directly instantiates the transceiver's primitives and the initialization logic. Switching to LiteICLink would simplify PHYs a lot (only the SATA specific part would be handled) and would also simplify adding support for new FPGA families: Artix7, ECP5, Ultrascale(+).

enjoy-digital commented 3 years ago

The PHYs are now already reusing the TX/RX init FSMs from LiteICLink which already simplifies things a lot and has enabled Artix7 support. Integrating more of LiteICLink will be evaluated to be sure it is useful and would not complicate the code more than current one.

enjoy-digital commented 3 years ago

The current solution seems to provide a good compromise. TX/RX init and PLL code are directly reused from LiteICLink and comparison of GTP/GTHE2_CHANNEL is still easy to do so it's easy to merge back changes/improvements.