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enjoy-digital / litesata

Small footprint and configurable SATA core
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uspsataphy.py, ussataphy.py: Fix PROGDIV to depend on data width #29

Closed rniwase closed 8 months ago

rniwase commented 8 months ago

I found that when setting the data_width to 32 in USLiteSATAPHY or USPLiteSATAPHY, LiteSATA does not operate.

This is because when the PHY buffer is disabled, the frequency of TXOUTCLK/RXOUTCLK does not change depending on the data width.

If the PHY data width is changed from 16 to 32, the frequency of TX/RXOUTCLK should be halved.

With this modification, I have adjusted the values of tx_progdiv_cfg/rx_progdiv_cfg to ensure the appropriate frequency of TXOUTCLK/RXOUTCLK based on the PHY data width.

enjoy-digital commented 8 months ago

Thanks @rniwase! This looks good and has been merged.