enjoy-digital
commented
6 months ago - [x] Integrate SI5351 core.
- [x] Test on hardware with 148.5MHz and 148.35MHz configurations.
- [x] Create 38.4MHz configuration (similar to SDR50) and test on hardware.
Closed enjoy-digital closed 6 months ago
enjoy-digital
commented
6 months ago enjoy-digital
commented
6 months ago 38.4MHz on all outputs (from wizard): Si5351B-RevB-Registers.txt
enjoy-digital
commented
6 months ago 38.4MHz on clk0:
# Si535x Registers Script
#
# Part: Si5351B
# Project File: <not saved>
# Includes Pre/Post Download Control Register Writes: Yes
# Creator: ClockBuilder Pro v4.12.0.3 [2024-03-06]
# Created On: 2024-05-15 15:41:06 GMT+02:00
# Address,Data
2,53h
3,00h
4,20h
7,01h
15,00h
16,0Fh
17,8Ch
18,8Ch
19,8Ch
20,8Ch
21,8Ch
22,8Ch
23,8Ch
26,00h
27,7Dh
28,00h
29,0Fh
30,DBh
31,00h
32,00h
33,11h
42,00h
43,04h
44,00h
45,09h
46,A0h
47,00h
48,00h
49,00h
90,00h
91,00h
149,00h
150,00h
151,00h
152,00h
153,00h
154,00h
155,00h
162,00h
163,00h
164,00h
165,00h
183,92h25MHz on clk0:
# Si535x Registers Script
#
# Part: Si5351B
# Project File: <not saved>
# Includes Pre/Post Download Control Register Writes: Yes
# Creator: ClockBuilder Pro v4.12.0.3 [2024-03-06]
# Created On: 2024-05-15 15:43:03 GMT+02:00
# Address,Data
2,53h
3,00h
4,20h
7,01h
15,00h
16,0Fh
17,8Ch
18,8Ch
19,8Ch
20,8Ch
21,8Ch
22,8Ch
23,8Ch
26,00h
27,01h
28,00h
29,10h
30,00h
31,00h
32,00h
33,00h
42,00h
43,01h
44,00h
45,10h
46,00h
47,00h
48,00h
49,00h
90,00h
91,00h
149,00h
150,00h
151,00h
152,00h
153,00h
154,00h
155,00h
162,00h
163,00h
164,00h
165,00h
183,92h38.4MHz requested generates 50MHz. 25MHz requested generate 32.1MHz.
-> Same ratio of 0.77...
enjoy-digital
commented
6 months ago 25MHz on clk0, no internal load:
/*
* Si5351B Rev B Configuration Register Export Header File
*
* This file represents a series of Skyworks Si5351B Rev B
* register writes that can be performed to load a single configuration
* on a device. It was created by a Skyworks ClockBuilder Pro
* export tool.
*
* Part: Si5351B Rev B
* Design ID:
* Includes Pre/Post Download Control Register Writes: Yes
* Created By: ClockBuilder Pro v4.12.0.3 [2024-03-06]
* Timestamp: 2024-05-15 16:28:06 GMT+02:00
*
* A complete design report corresponding to this export is included at the end
* of this header file.
*
*/
#ifndef SI5351B_REVB_REG_CONFIG_HEADER
#define SI5351B_REVB_REG_CONFIG_HEADER
#define SI5351B_REVB_REG_CONFIG_NUM_REGS 43
typedef struct
{
unsigned int address; /* 16-bit register address */
unsigned char value; /* 8-bit register data */
} si5351b_revb_register_t;
si5351b_revb_register_t const si5351b_revb_registers[SI5351B_REVB_REG_CONFIG_NUM_REGS] =
{
{ 0x0002, 0x53 },
{ 0x0003, 0x00 },
{ 0x0004, 0x20 },
{ 0x0007, 0x01 },
{ 0x000F, 0x00 },
{ 0x0010, 0x0F },
{ 0x0011, 0x8C },
{ 0x0012, 0x8C },
{ 0x0013, 0x8C },
{ 0x0014, 0x8C },
{ 0x0015, 0x8C },
{ 0x0016, 0x8C },
{ 0x0017, 0x8C },
{ 0x001A, 0x00 },
{ 0x001B, 0x01 },
{ 0x001C, 0x00 },
{ 0x001D, 0x10 },
{ 0x001E, 0x00 },
{ 0x001F, 0x00 },
{ 0x0020, 0x00 },
{ 0x0021, 0x00 },
{ 0x002A, 0x00 },
{ 0x002B, 0x01 },
{ 0x002C, 0x00 },
{ 0x002D, 0x10 },
{ 0x002E, 0x00 },
{ 0x002F, 0x00 },
{ 0x0030, 0x00 },
{ 0x0031, 0x00 },
{ 0x005A, 0x00 },
{ 0x005B, 0x00 },
{ 0x0095, 0x00 },
{ 0x0096, 0x00 },
{ 0x0097, 0x00 },
{ 0x0098, 0x00 },
{ 0x0099, 0x00 },
{ 0x009A, 0x00 },
{ 0x009B, 0x00 },
{ 0x00A2, 0x00 },
{ 0x00A3, 0x00 },
{ 0x00A4, 0x00 },
{ 0x00A5, 0x00 },
{ 0x00B7, 0x12 },
};
/*
* Design Report
*
* Overview
* ========
*
* Part: Si5351B
* Created By: ClockBuilder Pro v4.12.0.3 [2024-03-06]
* Timestamp: 2024-05-15 16:28:06 GMT+02:00
*
* Design Rule Check
* =================
*
* Errors:
* - No errors
*
* Warnings:
* - No warnings
*
* Design
* ======
* I2C Address: 0x60
*
* Inputs:
* IN0: 25 MHz
*
* Outputs:
* OUT0: 25 MHz
* Enabled LVCMOS 8 mA
* Offset 0.000 s
* OUT1: Unused
* OUT2: Unused
* OUT3: Unused
* OUT4: Unused
* OUT5: Unused
* OUT6: Unused
* OUT7: Unused
*
* Frequency Plan
* ==============
*
* PLL_A:
* Enabled Features = None
* Fvco = 900 MHz
* M = 36
* Input0:
* Source = Crystal
* Source Frequency = 25 MHz
* Fpfd = 25 MHz
* Load Capacitance = Not_Applicable
* Output0:
* Features = None
* Disabled State = StopLow
* R = 1 (2^0)
* Fout = 25 MHz
* N = 36
*
* Settings
* ========
*
* Location Setting Name Decimal Value Hex Value
* ------------ -------------- ----------------- -----------------
* 0x0002[3] XO_LOS_MASK 0 0x0
* 0x0002[4] CLK_LOS_MASK 1 0x1
* 0x0002[5] LOL_A_MASK 0 0x0
* 0x0002[6] LOL_B_MASK 1 0x1
* 0x0002[7] SYS_INIT_MASK 0 0x0
* 0x0003[7:0] CLK_OEB 0 0x00
* 0x0004[4] DIS_RESET_LOLA 0 0x0
* 0x0004[5] DIS_RESET_LOLB 1 0x1
* 0x0007[7:4] I2C_ADDR_CTRL 0 0x0
* 0x000F[2] PLLA_SRC 0 0x0
* 0x000F[3] PLLB_SRC 0 0x0
* 0x000F[4] PLLA_INSELB 0 0x0
* 0x000F[5] PLLB_INSELB 0 0x0
* 0x000F[7:6] CLKIN_DIV 0 0x0
* 0x0010[1:0] CLK0_IDRV 3 0x3
* 0x0010[3:2] CLK0_SRC 3 0x3
* 0x0010[4] CLK0_INV 0 0x0
* 0x0010[5] MS0_SRC 0 0x0
* 0x0010[6] MS0_INT 0 0x0
* 0x0010[7] CLK0_PDN 0 0x0
* 0x0011[1:0] CLK1_IDRV 0 0x0
* 0x0011[3:2] CLK1_SRC 3 0x3
* 0x0011[4] CLK1_INV 0 0x0
* 0x0011[5] MS1_SRC 0 0x0
* 0x0011[6] MS1_INT 0 0x0
* 0x0011[7] CLK1_PDN 1 0x1
* 0x0012[1:0] CLK2_IDRV 0 0x0
* 0x0012[3:2] CLK2_SRC 3 0x3
* 0x0012[4] CLK2_INV 0 0x0
* 0x0012[5] MS2_SRC 0 0x0
* 0x0012[6] MS2_INT 0 0x0
* 0x0012[7] CLK2_PDN 1 0x1
* 0x0013[1:0] CLK3_IDRV 0 0x0
* 0x0013[3:2] CLK3_SRC 3 0x3
* 0x0013[4] CLK3_INV 0 0x0
* 0x0013[5] MS3_SRC 0 0x0
* 0x0013[6] MS3_INT 0 0x0
* 0x0013[7] CLK3_PDN 1 0x1
* 0x0014[1:0] CLK4_IDRV 0 0x0
* 0x0014[3:2] CLK4_SRC 3 0x3
* 0x0014[4] CLK4_INV 0 0x0
* 0x0014[5] MS4_SRC 0 0x0
* 0x0014[6] MS4_INT 0 0x0
* 0x0014[7] CLK4_PDN 1 0x1
* 0x0015[1:0] CLK5_IDRV 0 0x0
* 0x0015[3:2] CLK5_SRC 3 0x3
* 0x0015[4] CLK5_INV 0 0x0
* 0x0015[5] MS5_SRC 0 0x0
* 0x0015[6] MS5_INT 0 0x0
* 0x0015[7] CLK5_PDN 1 0x1
* 0x0016[1:0] CLK6_IDRV 0 0x0
* 0x0016[3:2] CLK6_SRC 3 0x3
* 0x0016[4] CLK6_INV 0 0x0
* 0x0016[5] MS6_SRC 0 0x0
* 0x0016[6] FBA_INT 0 0x0
* 0x0016[7] CLK6_PDN 1 0x1
* 0x0017[1:0] CLK7_IDRV 0 0x0
* 0x0017[3:2] CLK7_SRC 3 0x3
* 0x0017[4] CLK7_INV 0 0x0
* 0x0017[5] MS7_SRC 0 0x0
* 0x0017[6] FBB_INT 0 0x0
* 0x0017[7] CLK7_PDN 1 0x1
* 0x001C[17:0] MSNA_P1 4096 0x01000
* 0x001F[19:0] MSNA_P2 0 0x00000
* 0x001F[23:4] MSNA_P3 1 0x00001
* 0x002C[17:0] MS0_P1 4096 0x01000
* 0x002F[19:0] MS0_P2 0 0x00000
* 0x002F[23:4] MS0_P3 1 0x00001
* 0x005A[7:0] MS6_P1 0 0x00
* 0x005B[7:0] MS7_P1 0 0x00
* 0x0095[14:0] SSDN_P2 0 0x0000
* 0x0095[7] SSC_EN 0 0x0
* 0x0097[14:0] SSDN_P3 0 0x0000
* 0x0097[7] SSC_MODE 0 0x0
* 0x0099[11:0] SSDN_P1 0 0x000
* 0x009A[15:4] SSUDP 0 0x000
* 0x00A2[21:0] VCXO_PARAM 0 0x000000
* 0x00A5[7:0] CLK0_PHOFF 0 0x00
* 0x00B7[7:6] XTAL_CL 0 0x0
*
*
*/
#endif25MHz on clk0, 10pF internal load, VCXO:
/*
*/
typedef struct { unsigned int address; / 16-bit register address / unsigned char value; / 8-bit register data /
} si5351b_revb_register_t;
si5351b_revb_register_t const si5351b_revb_registers[SI5351B_REVB_REG_CONFIG_NUM_REGS] = { { 0x0002, 0x33 }, { 0x0003, 0x00 }, { 0x0004, 0x10 }, { 0x0007, 0x01 }, { 0x000F, 0x00 }, { 0x0010, 0x2F }, { 0x0011, 0x8C }, { 0x0012, 0x8C }, { 0x0013, 0x8C }, { 0x0014, 0x8C }, { 0x0015, 0x8C }, { 0x0016, 0x8C }, { 0x0017, 0x8C }, { 0x0022, 0x42 }, { 0x0023, 0x40 }, { 0x0024, 0x00 }, { 0x0025, 0x10 }, { 0x0026, 0x00 }, { 0x0027, 0xF0 }, { 0x0028, 0x00 }, { 0x0029, 0x00 }, { 0x002A, 0x00 }, { 0x002B, 0x01 }, { 0x002C, 0x00 }, { 0x002D, 0x10 }, { 0x002E, 0x00 }, { 0x002F, 0x00 }, { 0x0030, 0x00 }, { 0x0031, 0x00 }, { 0x005A, 0x00 }, { 0x005B, 0x00 }, { 0x0095, 0x00 }, { 0x0096, 0x00 }, { 0x0097, 0x00 }, { 0x0098, 0x00 }, { 0x0099, 0x00 }, { 0x009A, 0x00 }, { 0x009B, 0x00 }, { 0x00A2, 0x33 }, { 0x00A3, 0x2C }, { 0x00A4, 0x02 }, { 0x00A5, 0x00 }, { 0x00B7, 0xD2 },
};
/*
*/
enjoy-digital
commented
6 months ago 25MHz on clk0, 10pF internal load:
/*
* Si5351B Rev B Configuration Register Export Header File
*
* This file represents a series of Skyworks Si5351B Rev B
* register writes that can be performed to load a single configuration
* on a device. It was created by a Skyworks ClockBuilder Pro
* export tool.
*
* Part: Si5351B Rev B
* Design ID:
* Includes Pre/Post Download Control Register Writes: Yes
* Created By: ClockBuilder Pro v4.12.0.3 [2024-03-06]
* Timestamp: 2024-05-15 16:51:14 GMT+02:00
*
* A complete design report corresponding to this export is included at the end
* of this header file.
*
*/
#ifndef SI5351B_REVB_REG_CONFIG_HEADER
#define SI5351B_REVB_REG_CONFIG_HEADER
#define SI5351B_REVB_REG_CONFIG_NUM_REGS 43
typedef struct
{
unsigned int address; /* 16-bit register address */
unsigned char value; /* 8-bit register data */
} si5351b_revb_register_t;
si5351b_revb_register_t const si5351b_revb_registers[SI5351B_REVB_REG_CONFIG_NUM_REGS] =
{
{ 0x0002, 0x53 },
{ 0x0003, 0x00 },
{ 0x0004, 0x20 },
{ 0x0007, 0x01 },
{ 0x000F, 0x00 },
{ 0x0010, 0x0F },
{ 0x0011, 0x8C },
{ 0x0012, 0x8C },
{ 0x0013, 0x8C },
{ 0x0014, 0x8C },
{ 0x0015, 0x8C },
{ 0x0016, 0x8C },
{ 0x0017, 0x8C },
{ 0x001A, 0x00 },
{ 0x001B, 0x01 },
{ 0x001C, 0x00 },
{ 0x001D, 0x10 },
{ 0x001E, 0x00 },
{ 0x001F, 0x00 },
{ 0x0020, 0x00 },
{ 0x0021, 0x00 },
{ 0x002A, 0x00 },
{ 0x002B, 0x01 },
{ 0x002C, 0x00 },
{ 0x002D, 0x10 },
{ 0x002E, 0x00 },
{ 0x002F, 0x00 },
{ 0x0030, 0x00 },
{ 0x0031, 0x00 },
{ 0x005A, 0x00 },
{ 0x005B, 0x00 },
{ 0x0095, 0x00 },
{ 0x0096, 0x00 },
{ 0x0097, 0x00 },
{ 0x0098, 0x00 },
{ 0x0099, 0x00 },
{ 0x009A, 0x00 },
{ 0x009B, 0x00 },
{ 0x00A2, 0x00 },
{ 0x00A3, 0x00 },
{ 0x00A4, 0x00 },
{ 0x00A5, 0x00 },
{ 0x00B7, 0xD2 },
};
/*
* Design Report
*
* Overview
* ========
*
* Part: Si5351B
* Created By: ClockBuilder Pro v4.12.0.3 [2024-03-06]
* Timestamp: 2024-05-15 16:51:14 GMT+02:00
*
* Design Rule Check
* =================
*
* Errors:
* - No errors
*
* Warnings:
* - No warnings
*
* Design
* ======
* I2C Address: 0x60
*
* Inputs:
* IN0: 25 MHz
*
* Outputs:
* OUT0: 25 MHz
* Enabled LVCMOS 8 mA
* Offset 0.000 s
* OUT1: Unused
* OUT2: Unused
* OUT3: Unused
* OUT4: Unused
* OUT5: Unused
* OUT6: Unused
* OUT7: Unused
*
* Frequency Plan
* ==============
*
* PLL_A:
* Enabled Features = None
* Fvco = 900 MHz
* M = 36
* Input0:
* Source = Crystal
* Source Frequency = 25 MHz
* Fpfd = 25 MHz
* Load Capacitance = Load_10pF
* Output0:
* Features = VCXO
* Disabled State = StopLow
* R = 1 (2^0)
* Fout = 25 MHz
* N = 36
*
* Settings
* ========
*
* Location Setting Name Decimal Value Hex Value
* ------------ -------------- ----------------- -----------------
* 0x0002[3] XO_LOS_MASK 0 0x0
* 0x0002[4] CLK_LOS_MASK 1 0x1
* 0x0002[5] LOL_A_MASK 0 0x0
* 0x0002[6] LOL_B_MASK 1 0x1
* 0x0002[7] SYS_INIT_MASK 0 0x0
* 0x0003[7:0] CLK_OEB 0 0x00
* 0x0004[4] DIS_RESET_LOLA 0 0x0
* 0x0004[5] DIS_RESET_LOLB 1 0x1
* 0x0007[7:4] I2C_ADDR_CTRL 0 0x0
* 0x000F[2] PLLA_SRC 0 0x0
* 0x000F[3] PLLB_SRC 0 0x0
* 0x000F[4] PLLA_INSELB 0 0x0
* 0x000F[5] PLLB_INSELB 0 0x0
* 0x000F[7:6] CLKIN_DIV 0 0x0
* 0x0010[1:0] CLK0_IDRV 3 0x3
* 0x0010[3:2] CLK0_SRC 3 0x3
* 0x0010[4] CLK0_INV 0 0x0
* 0x0010[5] MS0_SRC 0 0x0
* 0x0010[6] MS0_INT 0 0x0
* 0x0010[7] CLK0_PDN 0 0x0
* 0x0011[1:0] CLK1_IDRV 0 0x0
* 0x0011[3:2] CLK1_SRC 3 0x3
* 0x0011[4] CLK1_INV 0 0x0
* 0x0011[5] MS1_SRC 0 0x0
* 0x0011[6] MS1_INT 0 0x0
* 0x0011[7] CLK1_PDN 1 0x1
* 0x0012[1:0] CLK2_IDRV 0 0x0
* 0x0012[3:2] CLK2_SRC 3 0x3
* 0x0012[4] CLK2_INV 0 0x0
* 0x0012[5] MS2_SRC 0 0x0
* 0x0012[6] MS2_INT 0 0x0
* 0x0012[7] CLK2_PDN 1 0x1
* 0x0013[1:0] CLK3_IDRV 0 0x0
* 0x0013[3:2] CLK3_SRC 3 0x3
* 0x0013[4] CLK3_INV 0 0x0
* 0x0013[5] MS3_SRC 0 0x0
* 0x0013[6] MS3_INT 0 0x0
* 0x0013[7] CLK3_PDN 1 0x1
* 0x0014[1:0] CLK4_IDRV 0 0x0
* 0x0014[3:2] CLK4_SRC 3 0x3
* 0x0014[4] CLK4_INV 0 0x0
* 0x0014[5] MS4_SRC 0 0x0
* 0x0014[6] MS4_INT 0 0x0
* 0x0014[7] CLK4_PDN 1 0x1
* 0x0015[1:0] CLK5_IDRV 0 0x0
* 0x0015[3:2] CLK5_SRC 3 0x3
* 0x0015[4] CLK5_INV 0 0x0
* 0x0015[5] MS5_SRC 0 0x0
* 0x0015[6] MS5_INT 0 0x0
* 0x0015[7] CLK5_PDN 1 0x1
* 0x0016[1:0] CLK6_IDRV 0 0x0
* 0x0016[3:2] CLK6_SRC 3 0x3
* 0x0016[4] CLK6_INV 0 0x0
* 0x0016[5] MS6_SRC 0 0x0
* 0x0016[6] FBA_INT 0 0x0
* 0x0016[7] CLK6_PDN 1 0x1
* 0x0017[1:0] CLK7_IDRV 0 0x0
* 0x0017[3:2] CLK7_SRC 3 0x3
* 0x0017[4] CLK7_INV 0 0x0
* 0x0017[5] MS7_SRC 0 0x0
* 0x0017[6] FBB_INT 0 0x0
* 0x0017[7] CLK7_PDN 1 0x1
* 0x001C[17:0] MSNA_P1 4096 0x01000
* 0x001F[19:0] MSNA_P2 0 0x00000
* 0x001F[23:4] MSNA_P3 1 0x00001
* 0x002C[17:0] MS0_P1 4096 0x01000
* 0x002F[19:0] MS0_P2 0 0x00000
* 0x002F[23:4] MS0_P3 1 0x00001
* 0x005A[7:0] MS6_P1 0 0x00
* 0x005B[7:0] MS7_P1 0 0x00
* 0x0095[14:0] SSDN_P2 0 0x0000
* 0x0095[7] SSC_EN 0 0x0
* 0x0097[14:0] SSDN_P3 0 0x0000
* 0x0097[7] SSC_MODE 0 0x0
* 0x0099[11:0] SSDN_P1 0 0x000
* 0x009A[15:4] SSUDP 0 0x000
* 0x00A2[21:0] VCXO_PARAM 0 0x000000
* 0x00A5[7:0] CLK0_PHOFF 0 0x00
* 0x00B7[7:6] XTAL_CL 3 0x3
*
*
*/
#endif38.4MHz on all outputs + VCXO:
/*
* Si5351B Rev B Configuration Register Export Header File
*
* This file represents a series of Skyworks Si5351B Rev B
* register writes that can be performed to load a single configuration
* on a device. It was created by a Skyworks ClockBuilder Pro
* export tool.
*
* Part: Si5351B Rev B
* Design ID:
* Includes Pre/Post Download Control Register Writes: Yes
* Created By: ClockBuilder Pro v4.12.0.3 [2024-03-06]
* Timestamp: 2024-05-15 16:56:49 GMT+02:00
*
* A complete design report corresponding to this export is included at the end
* of this header file.
*
*/
#ifndef SI5351B_REVB_REG_CONFIG_HEADER
#define SI5351B_REVB_REG_CONFIG_HEADER
#define SI5351B_REVB_REG_CONFIG_NUM_REGS 88
typedef struct
{
unsigned int address; /* 16-bit register address */
unsigned char value; /* 8-bit register data */
} si5351b_revb_register_t;
si5351b_revb_register_t const si5351b_revb_registers[SI5351B_REVB_REG_CONFIG_NUM_REGS] =
{
{ 0x0002, 0x33 },
{ 0x0003, 0x00 },
{ 0x0004, 0x10 },
{ 0x0007, 0x01 },
{ 0x000F, 0x00 },
{ 0x0010, 0x2F },
{ 0x0011, 0x2F },
{ 0x0012, 0x2F },
{ 0x0013, 0x2F },
{ 0x0014, 0x2F },
{ 0x0015, 0x2F },
{ 0x0016, 0x2F },
{ 0x0017, 0x2F },
{ 0x0022, 0x42 },
{ 0x0023, 0x40 },
{ 0x0024, 0x00 },
{ 0x0025, 0x0E },
{ 0x0026, 0xE5 },
{ 0x0027, 0xF5 },
{ 0x0028, 0xBC },
{ 0x0029, 0xC0 },
{ 0x002A, 0x00 },
{ 0x002B, 0x01 },
{ 0x002C, 0x00 },
{ 0x002D, 0x09 },
{ 0x002E, 0x00 },
{ 0x002F, 0x00 },
{ 0x0030, 0x00 },
{ 0x0031, 0x00 },
{ 0x0032, 0x00 },
{ 0x0033, 0x01 },
{ 0x0034, 0x00 },
{ 0x0035, 0x09 },
{ 0x0036, 0x00 },
{ 0x0037, 0x00 },
{ 0x0038, 0x00 },
{ 0x0039, 0x00 },
{ 0x003A, 0x00 },
{ 0x003B, 0x01 },
{ 0x003C, 0x00 },
{ 0x003D, 0x09 },
{ 0x003E, 0x00 },
{ 0x003F, 0x00 },
{ 0x0040, 0x00 },
{ 0x0041, 0x00 },
{ 0x0042, 0x00 },
{ 0x0043, 0x01 },
{ 0x0044, 0x00 },
{ 0x0045, 0x09 },
{ 0x0046, 0x00 },
{ 0x0047, 0x00 },
{ 0x0048, 0x00 },
{ 0x0049, 0x00 },
{ 0x004A, 0x00 },
{ 0x004B, 0x01 },
{ 0x004C, 0x00 },
{ 0x004D, 0x09 },
{ 0x004E, 0x00 },
{ 0x004F, 0x00 },
{ 0x0050, 0x00 },
{ 0x0051, 0x00 },
{ 0x0052, 0x00 },
{ 0x0053, 0x01 },
{ 0x0054, 0x00 },
{ 0x0055, 0x09 },
{ 0x0056, 0x00 },
{ 0x0057, 0x00 },
{ 0x0058, 0x00 },
{ 0x0059, 0x00 },
{ 0x005A, 0x16 },
{ 0x005B, 0x16 },
{ 0x0095, 0x00 },
{ 0x0096, 0x00 },
{ 0x0097, 0x00 },
{ 0x0098, 0x00 },
{ 0x0099, 0x00 },
{ 0x009A, 0x00 },
{ 0x009B, 0x00 },
{ 0x00A2, 0xF2 },
{ 0x00A3, 0xFD },
{ 0x00A4, 0x01 },
{ 0x00A5, 0x00 },
{ 0x00A6, 0x00 },
{ 0x00A7, 0x00 },
{ 0x00A8, 0x00 },
{ 0x00A9, 0x00 },
{ 0x00AA, 0x00 },
{ 0x00B7, 0x12 },
};
/*
* Design Report
*
* Overview
* ========
*
* Part: Si5351B
* Created By: ClockBuilder Pro v4.12.0.3 [2024-03-06]
* Timestamp: 2024-05-15 16:56:49 GMT+02:00
*
* Design Rule Check
* =================
*
* Errors:
* - No errors
*
* Warnings:
* - No warnings
*
* Design
* ======
* I2C Address: 0x60
*
* Inputs:
* IN0: 25 MHz
*
* Outputs:
* OUT0: 38.4 MHz
* Enabled LVCMOS 8 mA
* Offset 0.000 s
* OUT1: 38.4 MHz
* Enabled LVCMOS 8 mA
* Offset 0.000 s
* OUT2: 38.4 MHz
* Enabled LVCMOS 8 mA
* Offset 0.000 s
* OUT3: 38.4 MHz
* Enabled LVCMOS 8 mA
* Offset 0.000 s
* OUT4: 38.4 MHz
* Enabled LVCMOS 8 mA
* Offset 0.000 s
* OUT5: 38.4 MHz
* Enabled LVCMOS 8 mA
* Offset 0.000 s
* OUT6: 38.4 MHz
* Enabled LVCMOS 8 mA
* Offset 0.000 s
* OUT7: 38.4 MHz
* Enabled LVCMOS 8 mA
* Offset 0.000 s
*
* Frequency Plan
* ==============
*
* PLL_B:
* Enabled Features = VCXO
* Fvco = 844.8 MHz
* M = 33.792
* Input0:
* Source = Crystal
* Source Frequency = 25 MHz
* Fpfd = 25 MHz
* Load Capacitance = Not_Applicable
* Output0:
* Features = VCXO
* Disabled State = StopLow
* R = 1 (2^0)
* Fout = 38.4 MHz
* N = 22
* Output1:
* Features = VCXO
* Disabled State = StopLow
* R = 1 (2^0)
* Fout = 38.4 MHz
* N = 22
* Output2:
* Features = VCXO
* Disabled State = StopLow
* R = 1 (2^0)
* Fout = 38.4 MHz
* N = 22
* Output3:
* Features = VCXO
* Disabled State = StopLow
* R = 1 (2^0)
* Fout = 38.4 MHz
* N = 22
* Output4:
* Features = VCXO
* Disabled State = StopLow
* R = 1 (2^0)
* Fout = 38.4 MHz
* N = 22
* Output5:
* Features = VCXO
* Disabled State = StopLow
* R = 1 (2^0)
* Fout = 38.4 MHz
* N = 22
* Output6:
* Features = VCXO
* Disabled State = StopLow
* R = 1 (2^0)
* Fout = 38.4 MHz
* N = 22
* Output7:
* Features = VCXO
* Disabled State = StopLow
* R = 1 (2^0)
* Fout = 38.4 MHz
* N = 22
*
* Settings
* ========
*
* Location Setting Name Decimal Value Hex Value
* ------------ -------------- ----------------- -----------------
* 0x0002[3] XO_LOS_MASK 0 0x0
* 0x0002[4] CLK_LOS_MASK 1 0x1
* 0x0002[5] LOL_A_MASK 1 0x1
* 0x0002[6] LOL_B_MASK 0 0x0
* 0x0002[7] SYS_INIT_MASK 0 0x0
* 0x0003[7:0] CLK_OEB 0 0x00
* 0x0004[4] DIS_RESET_LOLA 1 0x1
* 0x0004[5] DIS_RESET_LOLB 0 0x0
* 0x0007[7:4] I2C_ADDR_CTRL 0 0x0
* 0x000F[2] PLLA_SRC 0 0x0
* 0x000F[3] PLLB_SRC 0 0x0
* 0x000F[4] PLLA_INSELB 0 0x0
* 0x000F[5] PLLB_INSELB 0 0x0
* 0x000F[7:6] CLKIN_DIV 0 0x0
* 0x0010[1:0] CLK0_IDRV 3 0x3
* 0x0010[3:2] CLK0_SRC 3 0x3
* 0x0010[4] CLK0_INV 0 0x0
* 0x0010[5] MS0_SRC 1 0x1
* 0x0010[6] MS0_INT 0 0x0
* 0x0010[7] CLK0_PDN 0 0x0
* 0x0011[1:0] CLK1_IDRV 3 0x3
* 0x0011[3:2] CLK1_SRC 3 0x3
* 0x0011[4] CLK1_INV 0 0x0
* 0x0011[5] MS1_SRC 1 0x1
* 0x0011[6] MS1_INT 0 0x0
* 0x0011[7] CLK1_PDN 0 0x0
* 0x0012[1:0] CLK2_IDRV 3 0x3
* 0x0012[3:2] CLK2_SRC 3 0x3
* 0x0012[4] CLK2_INV 0 0x0
* 0x0012[5] MS2_SRC 1 0x1
* 0x0012[6] MS2_INT 0 0x0
* 0x0012[7] CLK2_PDN 0 0x0
* 0x0013[1:0] CLK3_IDRV 3 0x3
* 0x0013[3:2] CLK3_SRC 3 0x3
* 0x0013[4] CLK3_INV 0 0x0
* 0x0013[5] MS3_SRC 1 0x1
* 0x0013[6] MS3_INT 0 0x0
* 0x0013[7] CLK3_PDN 0 0x0
* 0x0014[1:0] CLK4_IDRV 3 0x3
* 0x0014[3:2] CLK4_SRC 3 0x3
* 0x0014[4] CLK4_INV 0 0x0
* 0x0014[5] MS4_SRC 1 0x1
* 0x0014[6] MS4_INT 0 0x0
* 0x0014[7] CLK4_PDN 0 0x0
* 0x0015[1:0] CLK5_IDRV 3 0x3
* 0x0015[3:2] CLK5_SRC 3 0x3
* 0x0015[4] CLK5_INV 0 0x0
* 0x0015[5] MS5_SRC 1 0x1
* 0x0015[6] MS5_INT 0 0x0
* 0x0015[7] CLK5_PDN 0 0x0
* 0x0016[1:0] CLK6_IDRV 3 0x3
* 0x0016[3:2] CLK6_SRC 3 0x3
* 0x0016[4] CLK6_INV 0 0x0
* 0x0016[5] MS6_SRC 1 0x1
* 0x0016[6] FBA_INT 0 0x0
* 0x0016[7] CLK6_PDN 0 0x0
* 0x0017[1:0] CLK7_IDRV 3 0x3
* 0x0017[3:2] CLK7_SRC 3 0x3
* 0x0017[4] CLK7_INV 0 0x0
* 0x0017[5] MS7_SRC 1 0x1
* 0x0017[6] FBB_INT 0 0x0
* 0x0017[7] CLK7_PDN 0 0x0
* 0x0024[17:0] MSNB_P1 3813 0x00EE5
* 0x0027[19:0] MSNB_P2 376000 0x5BCC0
* 0x0027[23:4] MSNB_P3 1000000 0xF4240
* 0x002C[17:0] MS0_P1 2304 0x00900
* 0x002F[19:0] MS0_P2 0 0x00000
* 0x002F[23:4] MS0_P3 1 0x00001
* 0x0034[17:0] MS1_P1 2304 0x00900
* 0x0037[19:0] MS1_P2 0 0x00000
* 0x0037[23:4] MS1_P3 1 0x00001
* 0x003C[17:0] MS2_P1 2304 0x00900
* 0x003F[19:0] MS2_P2 0 0x00000
* 0x003F[23:4] MS2_P3 1 0x00001
* 0x0044[17:0] MS3_P1 2304 0x00900
* 0x0047[19:0] MS3_P2 0 0x00000
* 0x0047[23:4] MS3_P3 1 0x00001
* 0x004C[17:0] MS4_P1 2304 0x00900
* 0x004F[19:0] MS4_P2 0 0x00000
* 0x004F[23:4] MS4_P3 1 0x00001
* 0x0054[17:0] MS5_P1 2304 0x00900
* 0x0057[19:0] MS5_P2 0 0x00000
* 0x0057[23:4] MS5_P3 1 0x00001
* 0x005A[7:0] MS6_P1 22 0x16
* 0x005B[7:0] MS7_P1 22 0x16
* 0x0095[14:0] SSDN_P2 0 0x0000
* 0x0095[7] SSC_EN 0 0x0
* 0x0097[14:0] SSDN_P3 0 0x0000
* 0x0097[7] SSC_MODE 0 0x0
* 0x0099[11:0] SSDN_P1 0 0x000
* 0x009A[15:4] SSUDP 0 0x000
* 0x00A2[21:0] VCXO_PARAM 130546 0x01FDF2
* 0x00A5[7:0] CLK0_PHOFF 0 0x00
* 0x00A6[7:0] CLK1_PHOFF 0 0x00
* 0x00A7[7:0] CLK2_PHOFF 0 0x00
* 0x00A8[7:0] CLK3_PHOFF 0 0x00
* 0x00A9[7:0] CLK4_PHOFF 0 0x00
* 0x00AA[7:0] CLK5_PHOFF 0 0x00
* 0x00B7[7:6] XTAL_CL 0 0x0
*
*
*/
#endifDone, but the fact that VCXO has to be enabled in SI5351 will need to be investigated.