about OrangePi 5 Max PCIe setting

[akioolin]

Hello All,

My current configuration is LiteX-M2SDR board + OrangePi 5 MAX.

I found the LiteX-M2SDR's LED is on and blinking a while during boot, but become blank after shell prompt appear.

Using lspci to check PCIe devices, but there is no detection of LiteX-M2SDR board.

After tracing the code of LiteX-M2SDR, the PCIe configuration seems using 4Lanes. Am I wrong?

For RPi 5 / CM4 , PCIe is Gen2, for RK3588 seems Gen3 on M.2 M-key slot.

What is my missing point ?

Many Thanks.

BR, Akio

[enjoy-digital]

Hi @akioolin,

the board you received should indeed be flashed with the 4-lanes bitstream. If possible, I would recommend doing a first test in classic computer with a M2 X4 connector just to verify enumeration with lspci or not. If enumerating, the issue will probably be related to OrangePi5 PCIe configuration. If not enumerating, I would recommend re-flashing the bitstream over JTAG with the M2 variant bitstreams available here: https://github.com/enjoy-digital/litex_m2sdr/issues/30

@meriac: Do you remember if anything specific was required on the OrangePI 5 Max to get the PCIe M2 connrector up?

Florent

[akioolin]

Hi, @enjoy-digital :

That is a very good idea. After testing, I'll report the result.

BR, Akio

[akioolin]

Hi, @enjoy-digital , All:

After some study and test, below is relevant updates need to be made to the Device Tree settings of OrangePi 5 Max. Please proceed in the following order.

cd /boot/dtb/rockchip sudo cp rk3588-orangepi-5-max.dtb rk3588-orangepi-5-max.orig.dtb sudo dtc rk3588-orangepi-5-max.dtb -o rk3588-orangepi-5-max.dts sudo joe rk3588-orangepi-5-max.dts Find num-lanes in the pcie@fe150000 section, change its setting value from <0x04> to <0x02>, and save it. sudo dtc rk3588-orangepi-5-max.dts -o rk3588-orangepi-5-max.dtb

After completion, reboot.

sync;sync;sync;sudo reboot

After logging into the system, confirm the following items to confirm whether the modification is successful.

dmesg |grep fe150000, confirm that the following message appears.

[6.267234] rk-pcie fe150000.pcie: invalid prsnt-gpios property in node [ 6.283941] rk-pcie fe150000.pcie: host bridge /pcie@fe150000 ranges: [ 6.283978] rk-pcie fe150000.pcie: IO 0x00f0100000..0x00f01fffff -> 0x00f0100000 [ 6.284028] rk-pcie fe150000.pcie: MEM 0x00f0200000..0x00f0ffffff -> 0x00f0200000 [ 6.284054] rk-pcie fe150000.pcie: MEM 0x0900000000..0x093fffffff -> 0x0900000000 [ 6.284115] rk-pcie fe150000.pcie: iATU unroll: enabled [ 6.284122] rk-pcie fe150000.pcie: iATU regions: 8 ob, 8 ib, align 64K, limit 8G [ 6.489335] rk-pcie fe150000.pcie: PCIe Linking... LTSSM is 0x3 [ 6.514894] rk-pcie fe150000.pcie: PCIe Linking... LTSSM is 0x4 [ 6.598237] rk-pcie fe150000.pcie: PCIe Link up, LTSSM is 0x130011 [ 6.598246] rk-pcie fe150000.pcie: PCIe Gen.2 x1 link up [ 6.598318] rk-pcie fe150000.pcie: PCI host bridge to bus 0000:00

dmesg |grep "pci 0000:00"

[6.598362] pci 0000:00:00.0: [1d87:3588] type 01 class 0x060400 [6.598375] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x3fffffff] [6.598383] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x3fffffff] [6.598390] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref] [6.598432] pci 0000:00:00.0: supports D1 D2 [6.598436] pci 0000:00:00.0: PME# supported from D0 D1 D3hot [6.605053] pci 0000:00:00.0: BAR 0: no space for [mem size 0x40000000] [6.605060] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x40000000] [6.605066] pci 0000:00:00.0: BAR 1: no space for [mem size 0x40000000] [6.605071] pci 0000:00:00.0: BAR 1: failed to assign [mem size 0x40000000] [6.605076] pci 0000:00:00.0: BAR 8: assigned [mem 0xf0200000-0xf02fffff] [6.605081] pci 0000:00:00.0: BAR 6: assigned [mem 0xf0300000-0xf030ffff pref] [6.605103] pci 0000:00:00.0: PCI bridge to [bus 01-ff] [6.605110] pci 0000:00:00.0: bridge window [mem 0xf0200000-0xf02fffff]

lspci, confirm that the following message appears. 0000:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd Device 3588 (rev 01) 0000:01:00.0 RF controller: Xilinx Corporation Device 7024 0003:30:00.0 PCI bridge: Rockchip Electronics Co., Ltd Device 3588 (rev 01) 0003:31:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller (rev 05) If "RF controller: Xilinx Corporation Device 7024" appears, the system has detected the LiteX-M2SDR board.

When all three of the above messages appear, you can proceed to the testing phase.

Testing stage:

Carry out relevant tests according to the following command sequence: sudo insmod ~/work/litex_m2sdr/software/kernel/litepcie.ko sudo chmod 666 /dev/m2sdr0

Using dmesg, confirm that the following message appears: [2999.724330] litepcie: loading out-of-tree module taints kernel. [2999.725121] litepcie 0000:01:00.0: \x1b[1m[Probing device]\x1b[0m [2999.725143] litepcie 0000:01:00.0: enabling device (0000 -> 0002) [2999.745151] litepcie 0000:01:00.0: Version LiteX-M2SDR SoC / m2 variant / built on 2024-09-05 17:46:29 [2999.745434] litepcie 0000:01:00.0: 1 MSI IRQs allocated. [2999.745500] litepcie 0000:01:00.0: Creating /dev/m2sdr0

Execute ~/work/litex_m2sdr/software/user/m2sdr_util info, the following message will appear: [> FPGA/SoC Info:

SoC Identifier : LiteX-M2SDR SoC / m2 variant / built on 2024-09-05 17:46:29. FPGA DNA: 0x0038cc0c7af9e854 FPGA Temperature: 49.5 °C FPGA VCC-INT: 1.00 V FPGA VCC-AUX: 1.79 V FPGA VCC-BRAM: 1.00 V FPGA Status: Operational

[> AD9361 Info:

AD9361 Product ID: 000a AD9361 Temperature: 0.0 °C

Execute ~/work/litex_m2sdr/software/user/m2sdr_rf, the following message will appear: Initializing SI5351 Clocking... Using internal XO for as SI5351 RefClk... Initializing AD9361 SPI... Initializing AD9361 RFIC... Setting Channel Mode to 2T2R. ad9361_init : AD936x Rev 2 successfully initialized Setting TX/RX Samplerate to 30.720000 MSPS. Setting TX/RX Bandwidth to 56.000000 MHz. Setting TX LO Freq to 98.200000 MHz. Setting RX LO Freq to 98.200000 MHz. Setting TX Gain to -20 dB. Setting RX Gain to 0 dB. Setting Loopback to 0 Enabling 16-bit mode.

At this point, the LiteX-M2SDR board installation has been completed.