R01 hardware/bringup issues.

[enjoy-digital]

• PicoEZ-Mate connector is not the correct one: pitch of 1.00mm vs 1.20mm expected. The connector can be desoldered and a proper 1.20mm connector soldered.
• SI5351 requires VCXO to be enabled to generate correct frequencies. Not an issue, just need to be aware of it.
• With PCIe Gen2 X4, link seems to be downgraded to X2, understand why. -> Only seen on initial test on a specific machine, was probably related to the machine or gateware.
• Add protection on baluns (throuth a custom heatsink?) or mount more resistant ones?
• SI5351: Connect SSEN to the FPGA instead of VCC, will allow swiching to the C variant, allowing CLKIN and then external Clock through the uFL connector.

[enjoy-digital]

Allow mounting SI5351C for CLKIN support instead of VC support.

-> Connecting SSEN pin to the FPGA will allow providing CLKIN from the FPGA (and from the uFL connector):