Closed tsmk94 closed 3 years ago
Thanks for the pull request, it is of course the proper solution, but does this really change anything in the resulting circuit? out
will be replaced either way. The difference I see using ?
is, that there would be an error if not all cases for the size variable are handled. Also some constraints posed by mkSizedFIFO
would play into it...
Anything else that didn't work before?
In the old solution, you got a compile error if passing zero as buffer size because the mkSizedFIFO cannot be created with zero size. The compiler seems to check this although it is replaced, as you said. Otherwise, I would not have noticed this issue at all.
Let read response FIFO in AXI4 Master be configurable as Bypass/Pipeline-FIFO like all other FIFOs as well.