Useful helpers for Bluespec developers.
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This is a collection of AXI 3 and 4 implementations. It contains the basic implementations for
in Master and Slave variants.
All implementations come with selectable FIFO buffers using mkPipelineFIFO
, mkBypassFIFO
, mkFIFO
or mkSizedFIFO
as well as the BRAM variants, depending on user selection.
In addition, the packet provides two AXI based primitives:
To get a local copy up and running follow these simple steps.
Have the Bluespec compiler installed.
git clone github.com/esa-tu-darmstadt/BlueAXI.git
BlueAXI
or a part of the packet in your Bluespec packet:
import BlueAXI :: *;
src
directory to your bsc
library path during compilation:
bsc ${OTHER_FLAGS} -p path/to/BlueAXI/src
Using AXI4 Lite is as simple as:
// Instantiate a AXI4 Lite Master with 14 address and 64 data bits using BypassFIFOs as buffers
AXI4_Lite_Master_Rd#(14, 64) m_rd <- mkAXI4_Lite_Master_Rd(0);
// Read from address 16 whenever possible
rule foo;
axi4_lite_read(m_rd, 16);
endrule
// Print the response
rule bar;
let r <- axi4_lite_read_response(m_rd);
printColorTimed(GREEN, $format("Address 16 is %d", r)); // From BlueLib
endrule
For more examples, please refer to the Documentation
See the open issues for a list of proposed features (and known issues).
Contributions are what make the open source community such an amazing place to be learn, inspire, and create. Any contributions you make are greatly appreciated.
git checkout -b feature/AmazingFeature
)git commit -m 'Add some AmazingFeature'
)git push origin feature/AmazingFeature
)Distributed under the MIT License. See LICENSE
for more information.
Embedded Systems and Applications Group - https://www.esa.informatik.tu-darmstadt.de
Project Link: https://github.com/esa-tu-darmstadt/BlueAXI