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firolightfog
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Yolow
Modules for VCV Rack
GNU General Public License v3.0
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CHSEL2 key 1 produces incorrect voltage
#43
firolightfog
opened
11 months ago
0
ROUTESEQ timing is off
#42
firolightfog
closed
12 months ago
1
QUANT12 calculation bug
#41
firolightfog
closed
1 year ago
1
SHEEP to be depriciated
#40
firolightfog
opened
1 year ago
0
FROMTO reset input to be checked
#39
firolightfog
closed
1 year ago
1
SAVEMEMORE timing bug
#38
firolightfog
opened
1 year ago
2
VULCAN needs cell labels
#37
firolightfog
opened
1 year ago
2
SAVEMEMORE reverse issue
#36
firolightfog
closed
1 year ago
2
Future plans on replacement modules
#35
firolightfog
closed
1 year ago
1
QUANT12 poly output is strange
#34
firolightfog
closed
2 years ago
1
ROTATRIG crashing
#33
firolightfog
opened
2 years ago
3
SHEEP linking start & end knobs is weirdo
#32
firolightfog
opened
2 years ago
0
SEQUIN needs a PW for ENBL
#31
firolightfog
opened
2 years ago
2
Add files via upload
#30
firolightfog
closed
2 years ago
0
PUSHME Ctrl-E freeze impact on timing
#29
firolightfog
closed
2 years ago
2
SHEEP buggy display
#28
firolightfog
closed
2 years ago
1
ROTATRIG new module
#27
firolightfog
closed
2 years ago
2
ELOOPS range switch review
#26
firolightfog
opened
2 years ago
0
QuantET new module
#25
firolightfog
closed
2 years ago
1
Update README.md
#24
firolightfog
closed
2 years ago
0
Add files via upload
#23
firolightfog
closed
2 years ago
0
General CPP update
#22
firolightfog
closed
2 years ago
0
General panel update
#21
firolightfog
closed
2 years ago
0
CELESTA & CELEI knob quickclick
#20
firolightfog
closed
2 years ago
2
CELESTA needs an undo history
#19
firolightfog
opened
2 years ago
1
Strange Rack crash
#18
firolightfog
closed
2 years ago
3
Strange Rack crash
#17
firolightfog
closed
2 years ago
1
CELESTA re-design (knobs, outputs)
#16
firolightfog
closed
2 years ago
2
CELESTA SUM output
#15
firolightfog
closed
2 years ago
1
CELESTA reset behaviors
#14
firolightfog
closed
2 years ago
1
Add files via upload
#13
firolightfog
closed
2 years ago
0
TRP1 no-clock, add-clock situation buggy
#12
firolightfog
opened
2 years ago
1
Adding modules
#11
firolightfog
closed
2 years ago
0
CHS8 voltage provider
#10
firolightfog
closed
2 years ago
1
CHS8 right-click crashing
#9
firolightfog
closed
2 years ago
1
CHS2 gates only
#8
firolightfog
closed
2 years ago
1
Delete temp.txt
#7
firolightfog
closed
2 years ago
0
Build fails (/src/9lives.cpp needs removing)
#6
SteveRussell33
closed
2 years ago
2
Correction of readme typos
#5
firolightfog
closed
2 years ago
0
Minor modifications
#4
firolightfog
closed
2 years ago
0
Alternate panels
#3
firolightfog
opened
2 years ago
1
SVG cleanup
#2
firolightfog
closed
2 years ago
0
Socket labels added
#1
firolightfog
closed
2 years ago
0