Zynq GEM Reference Designs for Ethernet FMC
Description
This project demonstrates the use of the Opsero Ethernet FMC (OP031) and Robust Ethernet FMC (OP041). The design uses the GMII-to-RGMII IP core to connect the hard GEMs of the Zynq PS to the Ethernet FMC PHYs. The designs target both the Zynq and ZynqMP devices and are illustrated by the block diagrams below.
Zynq Design
ZynqMP Design
Important links:
- Datasheets for Ethernet FMC and Robust Ethernet FMC
- The user guide for these reference designs is hosted here: Zynq GEM for Ethernet FMC docs
- To report a bug: Report an issue.
- For technical support: Contact Opsero.
- To purchase the mezzanine card: Ethernet FMC order page.
Requirements
This project is designed for version 2024.1 of the Xilinx tools (Vivado/Vitis/PetaLinux). If you are using an older version of the Xilinx tools, then refer to the release tags to find the version of this repository that matches your version of the tools.
In order to test this design on hardware, you will need the following:
- Vivado 2024.1
- Vitis 2024.1
- PetaLinux Tools 2024.1
- Ethernet FMC or Robust Ethernet FMC
- One of the target platforms listed below
- For designs containing AXI Ethernet Subsystem IP: Xilinx Soft TEMAC license
Target designs
This repo contains several designs that target various supported development boards and their FMC connectors. The table below lists the target design name, the number of ports supported by the design and the FMC connector on which to connect the mezzanine card. Some of the target designs require a license to generate a bitstream with the AMD Xilinx tools.
Zynq-7000 designs
| Target board | Target design | Ports | FMC Slot(s) | Standalone Echo Server |
PetaLinux | Vivado Edition |
|---|---|---|---|---|---|---|
| PicoZed 7030 | pz_7030 |
4x | LPC | :white_check_mark: | :white_check_mark: | Standard :free: |
| ZC706 | zc706_lpc |
4x | LPC | :white_check_mark: | :white_check_mark: | Enterprise |
| ZedBoard | zedboard |
4x | LPC | :white_check_mark: | :white_check_mark: | Standard :free: |
Zynq UltraScale+ designs
| Target board | Target design | Ports | FMC Slot(s) | Standalone Echo Server |
PetaLinux | Vivado Edition |
|---|---|---|---|---|---|---|
| PYNQ-ZU | pynqzu |
4x | LPC | :white_check_mark: | :white_check_mark: | Standard :free: |
| UltraZed-EG PCIe Carrier | uzeg_pci |
4x | LPC | :white_check_mark: | :white_check_mark: | Standard :free: |
| UltraZed-EV Carrier | uzev |
4x | HPC | :white_check_mark: | :white_check_mark: | Standard :free: |
| ZCU102 | zcu102_hpc0 |
4x | HPC0 | :white_check_mark: | :white_check_mark: | Enterprise |
| ZCU102 | zcu102_hpc1 |
3x | HPC1 | :white_check_mark: | :white_check_mark: | Enterprise |
| ZCU104 | zcu104 |
4x | LPC | :white_check_mark: | :white_check_mark: | Standard :free: |
| ZCU106 | zcu106_hpc0 |
4x | HPC0 | :white_check_mark: | :white_check_mark: | Standard :free: |
| ZCU111 | zcu111 |
4x | FMCP | :white_check_mark: | :white_check_mark: | Enterprise |
| ZCU208 | zcu208 |
4x | FMCP | :white_check_mark: | :white_check_mark: | Enterprise |
Software
These reference designs can be driven by either a standalone application or within a PetaLinux environment. The repository includes all necessary scripts and code to build both environments. The table below outlines the corresponding applications available in each environment:
| Environment | Available Applications |
|---|---|
| Standalone | lwIP Echo Server |
| PetaLinux | Built-in Linux commands Additional tools: ethtool, phytool, iperf3 |
Build instructions
Clone the repo:
git clone https://github.com/fpgadeveloper/ethernet-fmc-zynq-gem.gitSource Vivado and PetaLinux tools:
source <path-to-petalinux>/2024.1/settings.sh
source <path-to-vivado>/2024.1/settings64.shTo build the standalone lwIP echo server application (Vivado project and Vitis workspace):
cd ethernet-fmc-zynq-gem/Vitis
make workspace TARGET=zcu106_hpc0To build the PetaLinux image (Vivado project and PetaLinux):
cd ethernet-fmc-zynq-gem/PetaLinux
make petalinux TARGET=zcu106_hpc0Replace the target label in these commands with the one corresponding to the target design of your choice from the tables above.
Contribute
We strongly encourage community contribution to these projects. Please make a pull request if you would like to share your work:
- if you've spotted and fixed any issues
- if you've added designs for other target platforms
Thank you to everyone who supports us!
About us
This project was developed by Opsero Inc., a tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. Follow our blog, FPGA Developer, for news, tutorials and updates on the awesome projects we work on.