issues
search
gmcastil
/
basys3
A collection of source code and build scripts targeting the Digilent Basys3 FPGA board
MIT License
0
stars
0
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
UART skid buffer is not working yet
#9
gmcastil
opened
4 weeks ago
2
Uart fifo
#8
gmcastil
closed
2 months ago
1
Added TX and RX FIFO and started adding some error regisers and frame
#7
gmcastil
closed
2 months ago
0
Add FIFO to the UART transceivers
#6
gmcastil
closed
2 months ago
1
Finish the heartbeat / PWM RTL
#5
gmcastil
opened
3 months ago
0
Build a seven segment display module
#4
gmcastil
opened
3 months ago
0
Finish the UART RTL and verify in simulation
#3
gmcastil
closed
2 months ago
1
Need to make a clock and reset bus instead of manually routing clocks everywhere
#2
gmcastil
opened
3 months ago
0
Automate non project and project builds
#1
gmcastil
opened
3 months ago
0