hamsternz FPGA_DisplayPort issues - Githubissues

hamsternz / FPGA_DisplayPort

An implementation of DisplayPort protocol for FPGAs

MIT License

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Convert the core to Verilog

#3 mithro opened 6 years ago
1
See if simulation with Elephel GTX model is possible

#2 mithro opened 6 years ago
0
Corrected commented decimal value of V_start

#1 pwolf23 closed 8 years ago
0