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hkust-zhiyao
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RTLLM
An open-source benchmark for generating design RTL with natural language
MIT License
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RTLLM 2.0?
#9
CatIIIIIIII
opened
5 days ago
0
How to calculate timing for combinational logic circuits
#8
pierowu
opened
4 months ago
0
Missing design: risc_cpu
#7
sujay-pandit
opened
5 months ago
1
make error
#6
pierowu
closed
6 months ago
2
Can you give more details about how to perform logic synthesis?
#5
pierowu
closed
6 months ago
1
any pre-train model?
#4
Lucas-Wye
closed
6 months ago
1
fix: duplicaed variables
#3
LAD021
opened
8 months ago
0
fix: duplicated declaration
#2
LAD021
opened
8 months ago
0
Missing testbench.v files
#1
Nalaka1693
closed
10 months ago
3