The FASoC Program is focused on developing a complete system-on-chip (SoC) synthesis tool from user specification to GDSII. See more on our website.
FASoC tool can be operated in three modes, "Verilog", "Macro" and "Full" modes.
The provided generators can generate fully synthesizable verilog products using the user input specification file. The generated verilog will be derived from pre-characterized modules. Future releases of the tool will also generate a human readable constraint guidance that will aid in maximizing post layout design performance.
The macro generation mode will generate hard macros in addition to the verilog. These hard macros are synthesized and implemented versions of the verilog output using recommended constraints and physical guidance. This mode will require the commercial tools, access to the standard/cells, PDK and other tools. It will also require an automated flow (cadre flow) as well as several private files that are restricted due to NDA requirements.
Tool requirements:
Newer versions of the tools are expected, but not guaranteed to work.
Run the environment checker script to ensure all the tools are setup
make check_env
Ensure you have access to the required private repository for FASoC. Please contact ajayi@umich.edu if you need access
Ensure you have ssh keys setup for github. Instructions for generating and adding ssh keys can be found here.
Clone the FASoC repository
git clone git@github.com:idea-fasoc/fasoc.git
Initialize the submodules
cd fasoc
git submodule update --init --recursive
Setup the cadre flow to for your specific location. The "Macro/Full" modes currently requires TSMC65LP PDK and ARM standard cells. More instructions on how to setup this particular platform can be found in the Cadre Flow Guide
Change directory to the generator of interest and follow instructions in the readme
If you find this tool useful in your research, we kindly request to cite our paper:
T. Ajayi et al., “An open-source framework for autonomous soc design with analog block generation,” in 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC). IEEE, 2020.